DRV8353F: Questions regarding device GNDs and internal resistor values

Matt Calvo

Part Number: DRV8353F

Tool/software:

Hey BLDC team,

I have a customer working with the DRV8353FSRTAR for a new project and there are a couple of items in the datasheet that we're hoping you can help provide clarity on:

There are many various grounds mentioned throughout the datasheet (i.e. GND, AGND, PGND, BGND, & DGND). Can you please help to clarify what all of the grounds signify and whether any specific precautions should be taken in order to ensure a stable ground for this device? The only signals actually routed out to pins seem to be GND and AGND so are the other signals purely internal ground nets?
The datasheet also mentions "In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an internal resistor". Can you please share the value of these internal resistors as I don't think this is specified in the datasheet?

-Matt Calvo

over 1 year ago

0 Akshay Rajeev Menon over 1 year ago

TI__Mastermind 23266 points

Hey Matt,

Thank you for the question. I have assigned this to a team member to provide an update.

Best,

Akshay

0 Joshua Maize over 1 year ago

TI__Genius 12231 points

Hi Matt!

Please find my comments below:

Matt Calvo said:
There are many various grounds mentioned throughout the datasheet (i.e. GND, AGND, PGND, BGND, & DGND). Can you please help to clarify what all of the grounds signify and whether any specific precautions should be taken in order to ensure a stable ground for this device? The only signals actually routed out to pins seem to be GND and AGND so are the other signals purely internal ground nets?

For the DRV8353F there are indeed two separate ground planes: AGND (or "analog ground") which is typically recommended for lower voltage/current inputs, such as VREF, that may be more affected significantly by noisier signals,

The GND plane is a general plane that is system ground for the other higher voltage/current inputs/outputs, such as the input supply and power-stage ground connections. This separation is helpful for situations where the motor phase current could cause noise on more sensitive signals if they were connected on the same ground plane.

PGND ("power ground") and DGND ("digital ground") are very similar - PGND would be used for power plane inputs/outputs, while DGND would be used for more sensitive digital logic signals.

BGND I believe is a ground plane reserved for buck regulator inputs/outputs.

Matt Calvo said:
The datasheet also mentions "In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an internal resistor". Can you please share the value of these internal resistors as I don't think this is specified in the datasheet?

I believe the pulldown resistances are 150kOhm and are shown here in the given system block diagram: