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DRV8353: Regarding nFAULT of DRV8353HRTAT

Tatsuya Ichikawa
Prodigy 10 points
Part Number: DRV8353

Tool/software:

Dear BLDC team,

Regarding nFAULT of DRV8353HRTAT:

If the VVDS_OCP threshold in MOSFETVDS Overcurrent Protection (VDS_OCP) is exceeded for a duration longer than the tOCP_DEG deglitch time, the VDS_OCP event is recognized, and nFAULT goes low.
When nFAULT is low, it is expected that if a new rising edge of the PWM input is applied, the VDS_OCP event will be cleared, and nFAULT will go high.

Your question is, when nFAULT is low and you want to clear the VDS_OCP event, how long should elapse after nFAULT goes low before inputting a new rising edge of the PWM input?
I have attached an image. The MODE is [3x PWM] MODE.

Best regards,

Tatsuya Ichikawa

 

  • 0
    TI__Mastermind 23306 points

    Hey Ichikawa-san,

    Thank you for the question. I have assigned a team member to review the question and set timeline expectations.

    Best,

    Akshay

  • 0 in reply to Akshay Rajeev Menon
    Prodigy 10 points

    Hello Akshay,

    Thank you for confirming the contents.
    I'm looking forward to your answer.

    Best,

    Tatsuya Ichikawa

  • 0 in reply to Tatsuya Ichikawa
    TI__Expert 3020 points

    Hi Ichikawa-san,

    The fault will clear after a new rising edge on the PWM inputs, or after t_retry, whichever comes first. How quickly you can clear the fault will likely depend on the frequency of the PWM signal. What clock rate are you using for PWM? Note also that nFAULT will only go high after a delay through the digital logic after the new PWM input, so the time between nFAULT pulling low and then high will be different than the time between pulling low and the PWM input going high.

    Best,

    Davis

  • 0 in reply to Davis Jackson
    Prodigy 10 points

    Hello Davis,

    Thank you for providing an answer to my question.

    >What clock rate are you using for PWM?

      →The PWM frequency is 20 kHz.

    Best,

    Tatsuya Ichikawa

  • 0 in reply to Tatsuya Ichikawa
    TI__Expert 3020 points

    Hi Ichikawa-san, 

    Based on your PWM frequency, there will be at least 50us between recognizing the nFAULT and inputting a new rising edge on the PWM, which should be plenty of time. For the DRV8353, the SPI version of the device has an option for t_retry = 50us, so your PWM signal should be fine.

    Best,

    Davis

  • 0 in reply to Davis Jackson
    Prodigy 10 points

    Hello Davis,

    If a Fault is output at the rising edge of the PWM, it is indeed possible to clear the Fault within a maximum of 50us before the next rising edge occurs.

    However, there may be cases where a Fault is output at the midpoint of the PWM cycle. In this scenario, the time required to clear the Fault can be calculated using the following equation:
    50usec / 2 = 25usec

    What I want to know is how long minimum after the Fault is output can the Fault be cleared?

    Best,

    Tatsuya Ichikawa

  • +1 in reply to Tatsuya Ichikawa
    TI__Expert 3020 points

    Hi Ichikawa-san,

    Sorry, I had assumed you were monitoring for a fault and then propagating a PWM cycle in response. We don't specify a length of time after nFAULT goes low as the signal is an output and no deglitch is required. As long as the device recognizes that PWM has gone from low to high after nFAULT goes low, it should clear the fault. You can wait 1usec just to be safe. The length of time between the device recognizing the new PWM input and nFAULT releasing will depend on propagation through the digital logic.

    Best,

    Davis

  • 0 in reply to Davis Jackson
    Prodigy 10 points

    Hello Davis,

    Thank you for your reply. I have understood the content. 

    Best,

    Tatsuya Ichikawa