Other Parts Discussed in Thread: DRV8323
Tool/software:
Hello,
We wanted to get some clarification on the actual implications of the content covered as part of the Gate driver protections for DRV8334 in the datasheet.
Specifically about the series of events that happen after a gate driver fault occurs.
The datasheet for DRV8334 states the following for the PVDD Supply Undervoltage Lockout,
The datasheet says that once the fault occurs, the gate driver is disabled, and the fault state remains latched until its cleared through an SPI command.
When looking into the Gate driver DRV8323 datasheet, the following details were documented:
In the case of DRV8323, normal operation starts again once the fault condition is cleared. However, the bit continues to be latched even though normal operation resumed and needs to be cleared through the CLR_FLT bit or using a reset pulse. Our question is:
1) With the Gate Driver DRV8334, does the tool continue to remain shut down when the fault state is latched despite the PVDD_UV condition being cleared? Can it only run again upon clearing the latch through SPI command?
OR
2) Does to tool resume normal operation when the PVDD_UV condition is cleared and start running normally, despite the fault state remaining latched and not been cleared yet?
Thank you, Keith
