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DRV8305-Q1: fault condition

Yasushi Fujiwara
Genius 12725 points
Part Number: DRV8305-Q1

Tool/software:

Hello Experts,

My customer has question as follows. Would you answer them, please?
1. Recover from latched fault condition.
The latched fault condition will be indicated to the nFAULT-pin. To recover latched fault condition, customer need to write the CLR_FLTs bit asserted in register 0x9, bit D1. At this time, nFAULT-pin and gate driver are recovered to normal condition if latched fault condition is removed?

2. Power up sequence
When PVDD voltage is less than UVLO2, SPI communication is disabled, correct? Or If PVDD voltage is UVLO1<PVDD<UVLO2, SPI communication is still enabled?

3. PVDD_UVLO2
When device detect PVDD_UVLO2, Register 0x1(fault bit) and Register 0x3(bit 10) will be asserted, correct?

Best Regards,
Fujiwara

  • 0
    TI__Mastermind 23676 points

    Hey Fujiwara-san,

    Thank you for the question. I have assigned my teammate to provide feedback. Please expect an update next week.

    Best,

    Akshay

  • 0 in reply to Akshay Rajeev Menon
    TI__Genius 12725 points

    Hi Experts,

    Would you respond to my question, please?

    Best Regards,
    Fujiwara

  • 0
    TI__Genius 15665 points

    Hi Fujiwara-san,

    Yasushi Fujiwara said:
    1. Recover from latched fault condition.
    The latched fault condition will be indicated to the nFAULT-pin. To recover latched fault condition, customer need to write the CLR_FLTs bit asserted in register 0x9, bit D1. At this time, nFAULT-pin and gate driver are recovered to normal condition if latched fault condition is removed?

    the latch fault should be clear as well as the fault condition should be removed in order to return to normal operation.

    Yasushi Fujiwara said:
    2. Power up sequence
    When PVDD voltage is less than UVLO2, SPI communication is disabled, correct? Or If PVDD voltage is UVLO1<PVDD<UVLO2, SPI communication is still enabled?

    it looks like PVDD must be greater than VPVDD_UVLO1 for SPI to be ready to use.

    Yasushi Fujiwara said:
    3. PVDD_UVLO2
    When device detect PVDD_UVLO2, Register 0x1(fault bit) and Register 0x3(bit 10) will be asserted, correct?

    This is correct

    Regards,

    Yara

  • 0 in reply to Yara Al Shami
    TI__Genius 12725 points

    Hi Yara-san,

    If customer clear the fault conditions, /FAULT-pin will be "High" automatically? Or it needs to set "1" of CLR_FLTS bit 9 to resume /FAULT-pin is "High"? Also, DRV8705S-Q1 is same too?

    Best Regards,
    Fujiwara

  • 0 in reply to Yasushi Fujiwara
    TI__Genius 15665 points

    Hi Fujiwara-san,

    Any questions related to a brushed or stepper motor drivers like DRV8705S-Q1 please post a new thread regarding that question. I'll be able to assist with your brushless DC driver related questions.

    Latched NFAULT will not recover automatically when the customer clears the fault conditions. Once fault conditions are clear then the customer must either set the register bit CLR_FLTS back to 1 or issue an EN_GATE reset pulse.

    Regards,

    Yara