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DRV8329AEVM: DRV8329

turguy goker
Prodigy 230 points
Part Number: DRV8329AEVM
Other Parts Discussed in Thread: DRV8350, UCC3626, DRV8353

Tool/software:

We have a application for a 4 quadrant BLDC motor controller driver that is required to operate at 48DDC. It will need internal gate driver logic to interface with external N-FETS. It also need to have internal Hall Logic for internal commutation. External controller is micro processor and it will provide PWM logic 200kHz rate, with fault and direction and enable logic signals. We need current feedback to micro processor and also internal to this chip we need the cycle by cycle current limit functionality. Can you rec0mend a single chip solution please.

  • 0
    TI__Mastermind 26826 points

    Hi Turguy,

    Thank you for reaching out to us! The team will aim to provide a response next week.

    Regards,

    Anthony Lodi

  • 0
    TI__Expert 5578 points

    Hi Turguy,

    Based on what I understand from your application, I believe the 102V max, DRV8350/3 ("3" for 3x integrated CSAs) where you could drive the motor in 1x PWM mode while using integrated 6-step block commutation based on tables stored internally. The half bridge output states are managed by an external controller or connected directly to the hall sensor digital outputs from the motor.

    This is offered with both synchronous and asynchronous modes. For more information about the feature and commutation tables, please reference section 8.3.1.1.3 of the datasheet found here: https://www.ti.com/product/DRV8353 

    This device also has VDS overcurrent protection that operates in cycle-by-cycle mode by default. For more information about this protection feature, please reference section 8.3.6.3. It also supports the 200kHz PWM logic you are requesting.

    Best,

    Robert

  • 0 in reply to Robert Wedan
    Prodigy 230 points

    Thanks for the reply. Yes this seems like a good candidate. However I don't see 3 Phase Hall signals for internal commutation control present with this ASIC. as i understand I or user must provide the Hall commutation by the external controller and feeding the PWM H / L controls to each one of the 3 phase logic. I was hoping that ASIC has the internal Hall commutation logic such that i present a signal PWM control and ASIC internally decides which phases to feed the PWM to. Any comments/

  • 0 in reply to turguy goker
    TI__Expert 5578 points

    Hi Turguy,

    The hall states can be managed by directly feeding into the driver pins INLA, INHB, and INLB. The driver will use these inputs to commutate based on the tables in this section of the datasheet. See the notes from section 8.3.1.1.3 of the datasheet:

    There is an option to provide hall state from external controller, but this is not required as Figure 23 shows above.

    Best,

    Robert

  • 0 in reply to Robert Wedan
    Prodigy 230 points

    Nice thanks. I need to study this feature. thanks for point this out.

  • 0 in reply to turguy goker
    TI__Expert 5578 points

    Hi Turguy,

    No problem! If this has resolved your questions, please help by marking this thread as resolved. If you have any additional questions, you can reply to this thread or start a new one. 

    Best,

    Robert

  • 0 in reply to Robert Wedan
    Prodigy 230 points

    Does the internal table in Drv8350 support 4 quadrant mode operation using Hall Sensors?

  • 0 in reply to turguy goker
    TI__Expert 5578 points

    Hi Turguy,

    4 quadrant operation, and specifically reverse regenerative braking, is a highly complex algorithm in which we need to precisely control the current in and out of each of the gates. This level of complexity is not available in 1x PWM where the device is just cycling through the stages based on the hall states.

    In 1x PWM mode, the INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this feature is not required.

    Just to double check, by 4 quadrant operation, you mean you want to do reverse regenerative braking, correct? This would be commutating the FETs in the reverse direction to actively spin down the motor and having the current flow back into the supply. This is a highly specific algorithm feature. Can you provide more details around the use case you are trying to accomplish?

    Best,

    Robert

  • 0 in reply to Robert Wedan
    Prodigy 230 points

    Application is moving a load Up and Down with position loop where current is controlled and accelerating and decelerating in Up and Down direction where 4 quadrant is needed. Here is the basic description of the system requirement. Note old UCC3626 was able to do this but I am looking for a new device.

    The 4-quadrant operation of a 3-phase power bridge driving a BLDC motor using Hall commutation logic is the ability of the system to operate in all four quadrants of the torque-speed plane. Basically:

    1. First Quadrant (Forward Motoring)
    • Operation: The motor runs in the forward direction with positive torque and speed.
    • Action: The power bridge supplies positive voltage and current to the motor windings. Hall sensors provide feedback to control the commutation sequence, ensuring proper motor rotation.
    • Application: This is the normal driving mode where the motor provides forward propulsion.
    1. Second Quadrant (Forward Braking/Regeneration)
    • Operation: The motor is still running forward, but the torque is negative (braking), causing the motor to decelerate.
    • Action: The power bridge allows the motor to act as a generator, feeding energy back to the power source. The Hall sensors continue to control the commutation, but current is now flowing in the opposite direction.
    • Application: This is used when you want to decelerate the motor while recovering energy (regenerative braking).
    1. Third Quadrant (Reverse Motoring)
    • Operation: The motor runs in reverse, with negative speed and torque.
    • Action: The power bridge applies reverse voltage to the motor, driving it in the opposite direction. Hall commutation logic is adjusted to rotate the motor in reverse.
    • Application: This mode is used when reverse propulsion is needed.
    1. Fourth Quadrant (Reverse Braking/Regeneration)
    • Operation: The motor is running in reverse, but the torque is positive (braking), causing the motor to decelerate.
    • Action: Similar to forward braking, the motor acts as a generator, feeding energy back to the power source. The power bridge and Hall sensors work to control the reverse braking process.
    • Application: This mode is used when the motor needs to be decelerated while running in reverse, potentially recovering energy.

    In all four quadrants, the Hall commutation logic helps to control the switching of the power bridge to ensure that the motor phases are energized in the correct sequence for smooth operation, whether in motoring or braking modes. This enables precise control over both direction and braking, essential for applications requiring dynamic performance.

  • 0 in reply to turguy goker
    TI__Mastermind 26826 points

    Hi Turguy,

    The DRV8350/3 should be able to operate in all 4 quadrants while using 1x PWM mode. For 1xPWM mode, the INHC input becomes a direction input which can be used to flip the commutation sequence in reverse based on the hall states. The microcontroller can use this direction input to operate either in the first quadrant or the third quadrant, and it could also switch the direction pin while the motor is running in order to reverse the commutation sequence which would begin to brake the motor and have a regenerative effect. The microcontroller would need to determine when to change the direction state based on the quadrant of operation and what PWM duty cycle to apply to achieve the desired acceleration/deceleration time.

    Regards,

    Anthony Lodi

  • 0 in reply to Anthony Lodi
    Prodigy 230 points

    Can you also explain the difference between 8323 and 8353 Motors drivers for using Halls and 4 Quadrant mode operation. Note we plan to use a digital current loop to control torque in 4 quadrant mode. Also for both 8353 and 8323 IC's I see current feedback amplifiers for external controller use however I cant see  in the specs a cycle by cycle current limit function which these devices typically needs to provide. Can you help with this feature also.  Thank you for your support. Learning a lot from your feedback. Slight smile

  • 0 in reply to turguy goker
    TI__Mastermind 26826 points

    Hi Turguy,

    Between 8323 and 8353 relating to 1xPWM mode, there is no difference in capability. 1x PWM mode implementation is the same on both these devices, including the ability to reverse commutation direction with the DIR input (INHC).

    One major difference between the 8323 and 8353 is that the 8353 is targeted for 48V applications while the 8323 is targeted for 36V or below applications from an abs max perspective. 

    One thing to note: For the SPI variants the default PWM mode is 6xPWM mode, so it will need to be reconfigured to 1xPWM mode at each powerup/device reset (https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1209741/faq-when-do-i-need-to-reconfigure-my-motor-driver-s-register-settings). As a result, if it is possible to keep all inputs low while enabling the driver that will help avoid unintentional FET turnon due to the driver initially interpreting the inputs as 6xPWM mode. For the hardware variant, PWM mode is configured by a resistor on a pin instead of over SPI and therefore the device automatically selects the configured PWM mode at powerup (in your case, 1xPWM).

    Regards,

    Anthony Lodi

  • 0 in reply to Anthony Lodi
    Prodigy 230 points

    Thanks very much Anthony. Can you please also explain the current Fbk and cycle by cycle current limit function where the limit needs to be set by external controller

  • +1 in reply to turguy goker
    TI__Mastermind 26826 points

    Hi Turguy,

    The DRV8353 has 3 integrated current sense amplifiers for sensing the voltage drop across a shunt resistor. The output of the amplifiers can be fed back to an ADC for current measurement. The gain is configurable. The current sense amplifier specifications can be found under the electrical characteristics table of the datasheet. Section 8.3.4 of the datasheet goes into detail on the CSA feature of the device. The cycle by cycle overcurrent protection feature is described in section 8.3.6.3, it is looking at the VDS voltage drop across the FET and a trip threshold is selected based on the desired trip current. The available VDS voltage trip thresholds (VVDS_OCP) can be found in the electrical characteristics table of the datasheet. 

    Let me know if you have any additional questions after looking over those sections!

    Regards,
    Anthony Lodi