DRV8705-Q1: Register setting

Hello Fujiwara-san,

Yasushi Fujiwara said:

1. SSC_DIS bit in IC_CTRL Register (Address = 4h)
Regarding SSC_DIS bit in IC_CTRL Register (Address = 4h), SSC is enabled if this bit is set "0"? Or it is set disable SSC? Also if SSC is set enable, is there any concern to use this device?

Yes correct. SSC_DIS is the SSC disable bit. SSC_DIS = 1 will disable SSC feature. To enable SSC the SCC_DIS must be 0. There's no concern whether SSC is enabled or disabled. When enabled the internal clock will be modulated and help mitigate the peak EMI level and spread it to a lower level over a small range of frequencies. 

Yasushi Fujiwara said:

2. LOCK bits in IC_CTRL Register (Address = 4h)
Regarding LOCK bits in IC_CTRL Register (Address = 4h), what is purpose this bits? Also if LOCK bits are set to "110b" and other bits are set by same timing of LOCK bits, other bits will not be set? if LOCK bits are set "011b" and other bits are set by same timing of LOCK bits, other bits will be set?

When LOCK bits are set to "110b" all the control registers will be locked with no further write access and will ignore any write to control registers attempts. In order to modify control registers setting the LOCK bits must be set to "011b" the unlock setting which is also the default setting at power on. The IC_CTRL will accept a unlock setting when the LOCK bits are set as well. This will allow the user the unlock the LOCK bits when necessary. Thank you.

Regards, Murugavel