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DRV8962: T_effective to use for measure of effective PWM

Christina Lim
Expert 6305 points
Part Number: DRV8962

Tool/software:

Hi, 

I have a query regarding the DRV8962 on the estimation of the effective PWM duty cycle. The datasheet listed these parameters which I think should be the major factors affecting the accuracy of the duty cycle.

 

We are using the DRV8962 as 4 independent half bridge drivers, not in H-Bridge config. I assume the effective Ton/ Toff will be Ton/ Toff minus the delay time contributed by propagation delay + rise/fall time + dead time. And the effective duty cycle will be Ton/( Ton + Toff) after minus the delay times.

The confusion comes from whether t5/t6 include the rise/fall time and dead time. I did not take t1/t2/t3/t4 into consideration assuming enable pins are already enabled long before switching.

 

Teffective = Ton/ Toff - t5/t6 since tRF and tD are included in t5/t6

Teffective = Ton/ Toff – (t5/t6 + tRF + tD) as tRF and tD are excluded in t5/t6

 

Please let me know if any of the above understanding is incorrect. Thank you.

  • 0
    TI__Mastermind 44525 points

    Hi Christina,

    Christina Lim said:
    We are using the DRV8962 as 4 independent half bridge drivers, not in H-Bridge config. I assume the effective Ton/ Toff will be Ton/ Toff minus the delay time contributed by propagation delay + rise/fall time + dead time. And the effective duty cycle will be Ton/( Ton + Toff) after minus the delay times.

    A you may notice the INx high to OUTx high delay and INx low to OUTx low delay are symmetrical at 600 ns typical. This means there will be no impact to PWM duty cycle because of the delay - the low delay will cancel the effect of high delay. The rise/fall time will affect the lowest duty cycle that can be output based on the PWM frequency. The minimum duty cycle on time will be defined by tRISE + tFALL. The dead time will contribute to the PWM error -or- effective PWM duty cycle. 

    Christina Lim said:
    The confusion comes from whether t5/t6 include the rise/fall time and dead time. I did not take t1/t2/t3/t4 into consideration assuming enable pins are already enabled long before switching.

    t5/t6 does not include the rise/fall time and dead time. Yes if the enable is active already t1 to t4 does not apply for the calculation. I hope this helps. Thanks.

    Regards, Murugavel 

  • 0 in reply to Murugavel4637
    TI__Expert 6305 points

    Hi Murugavel, 

    Thanks for the feedback. 

    At max. recommended PWM frequency of 200kHz, tR + tF  = 140ns (MODE =1) would mean min. duty cycle = 140ns * 200kHz * 100% = 2.8%?

    Is there an TI application report that illustrates the high/low delay times, rise/fall times, and the 2 dead times (HS FET-off to LS FET-on and LS FET-off to HS FET-on) in relation to the PWM input and output waveforms for DRV8962? Taking reference from the TI application report SLVAF84 Figures 2-4 and 2-6, the dead times may or may not be included in the high/low delay times depending on input rising/falling.

     

    My confusion comes from this application note and I originally thought the propagation delay times, dead times and rise/fall times will reduce the on-time and increase the off-time of a period, resulting in reduced effective duty cycle.

    Thanks,

    Christina 

  • 0 in reply to Christina Lim
    TI__Mastermind 44525 points

    Hi Christina,

    Christina Lim said:
    At max. recommended PWM frequency of 200kHz, tR + tF  = 140ns (MODE =1) would mean min. duty cycle = 140ns * 200kHz * 100% = 2.8%?

    Yes this is the theoretical minimum assuming no additional L-C time constants at play at the output load side which could increase the minimum duty cycle. But, yes this the calculation. At this duty cycle the output waveform will just be a triangular with peak equal to square wave peak. Above 2.8% the plateau would appear at the output.  

    Christina Lim said:
    Is there an TI application report that illustrates the high/low delay times, rise/fall times, and the 2 dead times (HS FET-off to LS FET-on and LS FET-off to HS FET-on) in relation to the PWM input and output waveforms for DRV8962?

    No specific application report with this. Please note this theory applies to all PWM output drives not just specific to one device. It is general electronics theory.

    Christina Lim said:
    My confusion comes from this application note and I originally thought the propagation delay times, dead times and rise/fall times will reduce the on-time and increase the off-time of a period, resulting in reduced effective duty cycle.

    Let's separate out propagation delay and dead time impact on the duty cycle. You are correct about the propagation delay. For devices with symmetrical on time and off time propagation delay such as the DRV8962 the on time delay and off time delay compensate each other so net impact on PWM on time is close to zero or no impact. This also depends on how you see the PWM output. The plateau would be smaller but the effect of average voltage would be the same. 

    However the dead time manifests differently. It will add to the PWM off time depending on the input to output PWM polarity to the load. See below example. The dead time can effectively reduce the PWM frequency by a small amount because the tOFF will be extended by 2x dead time. This also results with a different value for the duty cycle. Keep in mind the impact are subtle because the DRV8962 dead time specification is only 300 ns, typical. The highest impact would be at the maximum PWM input frequency of 200 kHz. At 20 kHz the impact would be much smaller. See below example illustration. Thank you.

    Regards, Murugavel