DRV3256-Q1: Cleat Fault

Hemanth,

Could you tell us the complete readback from the following registers during the fault state?

0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, and 0x08.

This will help us identify which fault is occurring and the relevant node to be checked.

Regards,

-Adam

Dear Adam,

The below case is one of my observations.

If the DH_OV is triggered as fault as per mode selection (VDHCP > VDH_OV), this fault status shown in status register IC_STAT_3 --> DH_OV -->1(indicates overvoltage fault on DHCP).

 IC_STAT_3 = 80h

After the fault was removed/ the VDHCP voltages falls to safer level, need reset the fault status for gate driver operation. where we are trying to reset, by clearing the faults through IC_CTRL_1 --> CLR_FLT--> 1b1.

IC_CTRL_1 = 87.

The fault is not cleared through this command ((IC_CTRL_1 --> CLR_FLT--> 1b1)).

Hermanth,

Can you show us a waveform including DHCP voltage, when the error occurs, and when the SPI transactions are sent or received to clear the fault.

The fault condition needs to be corrected (DHCP less than VDH_OV) before you can issue the clear faults command and the fault can be cleared.

Regards,

-Adam

Hi adam, as per your request attached images in below along with description.

The graph in image represents the battery voltage fault tigger level and then falls to nominal voltage.

The Status register of IC_STAT_3 --> DH_OV --> 1 ((95h) indicates the fault status of overvoltage fault on DHCP

This image represents the configuration of IC_CTRL_1 --> CLR_FLT --> 1(86)

Image represents the new data is configuring into the IC_CTRL_1 --> 87h

Image represents Data sent through the SPI for IC_CTRL_1 and unchanged value in IC_CTRL_1 in gate driver.

Hemanth,

Thanks for this info, I will check it with the team and get back to you tomorrow.

Regards,

-Adam

Hi adam any update?

Hemanth,

Sorry for the delay during the holidays.

I will check this with the team and get back to you by end of day tomorrow.

Regards,

-Adam

Hi adam,

we are looking for your response.

Hemanth,

I need to check on this with the team tomorrow, I will get back to you by end of day.

Regards,

-Adam

Hi Adam,

Any update on my query.

Sorry for the delay, I am still working on this, I will get back to you this week.

Regards,

-Adam

Hemanth,

Is the issue that you cannot readback 0x87 from register IC_CTRL_1? Or is IC_STAT_3 not changing after you write 0x87 to IC_CTRL_1?

You will not be able to read 0x87 from IC_CTRL_1 because it auto clears as soon as it is written.

The only way to debug this further is if you can connect your scope or a logic analyzer to the SPI lines so that we can inspect the communication between the DRV and MCU.

Regards,

-Adam