DRV8353: DRV8353 and PWM tables

Thankyou Joshua. 

I am a bit puzzled here Josh. You said:

" This is correct - when INHX and INLX are both low then the MOSFETs have no significant gate signal (gate is neither pulled high or pulled to GND) and the outputs/SHx are essentially floating at high impedance. "

Based on this I understand that GLx and GHx signals are noted as "L" in table 1 when inputs are both L or both H, inputs being INLx and INHx; this condition per your explanation L means neither high or true low. 

Yet when same inputs are Low/High or High /Low then GLx and GLHx are either High which means drive gate gigh and turn on FET or Low (same L symbol as above) but this time actual turn off the FETs.

I am quite puzzled between the 2 conditions of L as shown in table.

When Halls based PWM commutation transitions from High to Low which will be connected to the INHx and INLx signals of 8353, we expect fet gates to be kept actively in Off stage by their gates not to be floating. I think I need more information to understand how fets are turned on anbd off with Table 1. 

below picture is the signals we will be generating from UCC3626 with QUAD =1 case. I like to know what 8353 will provide at GLx and GHx output. 

High I like FTe to turn on by gate to source high voltage and L I like FET to turn off by its Gate to source voltage low. Can you please explain this if i use Table 1.

Note I dont want to use table 5 because it does not provide shoot through protection; maybe I am wrong.

Hi Joshua

A different way to ask same question using 8353 Gate Drive Circuit diagram from the specification pdf document:

Mission is to use Table 1 as shown below to commutate BLDC motor 3 phase FET bridge using Unitrode UCC3626 (now TI) controller as shown above

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Below is an excerpt from the 8353 specification, detailing the design and functionality of the gate driver circuitry.

Question: I’d like clarification on the detailed operation of the gate driver under the conditions described in Table 1:

• Condition: Both INL and INH are low (L).
  • According to Table 1:
    • The gate-to-source voltage (GH to SH) for the high-side external FET is low, meaning the high-side external FET remains off.
    • And gate-to-source voltage (GL to SL) for the low-side external FET is also low, meaning the low-side external FET remains off.
    • Therefore both external FETs are off, resulting in the motor winding (SHx) being in a high-impedance (Hi-Z) state, which aligns with expectations.
    • Also, High side external fet source and low side external fet drain connection is connected to the 8353 SH pin.

Follow-up Details:

• In this state, the Gate driver internal lower FET on the high-side remains on with low impedance. This fet sees a load that includes includes a 150 kΩ internal resistor in parallel with the external high side FET's gate-to-source capacitance (which has no charge under these conditions).
• A similar situation applies to the low-side gate driver circuitry for the lower external FET.

Assumption: This condition, where the lower internal FET for the high-side remains on with low impedance, can persist for extended periods indefinitely because both INH and INL inputs to the 8353 are held low. Same can be stated for the lower internal FET for the low-side internal gate droiver droiving low side external FET.

Question: Is this explanation accurate, particularly regarding the behavior of the internal lower FETs for both low and high side and the long-term stability of this condition if we kept INH and INL both low at the inputs of 8353?

Note I used only the L and L row but same questions can be composed for other 3 rows of table #1.

Hi Turguy,  

Thank you for your additional comments/clarifications. Please allow me to follow-up later today with a full response. 

Best Regards,

-Joshua

Thanks Joshua. I understand but I still want to verify that External FETS are not turned off by internal 150K resistors only but with internal chip gate drive fets as shown below in annotated picture. Please see my explanation and tell me if what I draw here is correct or not. If not please make the correction.

I think Point A in my annotation is HiZ state with both external FETS Off. But lets say top external FET gat to source Capacitor which is crucial to determine external fet On or Off condition is still tied to 8353 SHx pin by a physical trace. If 8353 SHx is also HiZ then external Fet cate to source cap is floating . This may mean only thing keeping this cap from having any charge os 8353 internal R 150K. This sounds very suspicious to me. Why not 8353 internal Fet which i show in my annotation as Top Lower Internal FET is not held on providing low impedance to external FET gat to source Capacitor so this can never charge; this way of impedance is much lower than 150K. I like to know more about this please.

Also example:

Assume we have INHx = H and INLx is Low. This means top external fet is on and bottom is Off Point A is at 48 volts. In this condition Top higher internal Fet is in On condition to provide high gate to source voltage like 10 volts.

Now both inputs go Low and low which can be a real condition. I assume Top Lower Internal Fet actually turning on to physically discharge the External FET gate to source capacitor, not the 150K resistor. Do you now mean that this internal fet actually turns off which is what i am puzzled with.

I see the role of internal 150K is a protection mode not an active turning of external fets mode; since discharging gate cap with 150K is way too long of an event. 

Please comment; also maybe we need to set a meeting to talk this since we are going back and forth.  My concwrn is abased on your answers the role of 150K; I think this aa safety just in case role not an actively keep Gate to Source cap low when things are fucntional. I am happy to have a meeting Joshua.

Regards

TG

Hi Turguy,  

Thank you for the response here. I think i better understand your question now and will follow-up today with a further response.  If there's still confusion then I would also be happy to have a meeting to discuss this topic at the start of next week since i will be unavailable due to the holidays.  

Best Regards, 

-Joshua