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DRV8300-Q1: The deadtime configuration problem

Tommy
Intellectual 515 points
Part Number: DRV8300-Q1

Tool/software:

Hi E2E，

We are verifying the design of the DRV8300-Q1 in a water-pump project.

This is the output waveform of the high-side and low-side gate of the DRV8300-Q1 at open load.

My question is:

Why is there a step when the gate drive voltage of the high-side drops down from around 24V?

Is it because of the discharge of the charge pump boost capacitor?

We suspect that the time of the step should be related to the deadtime set by our software,the deadtime is set to 1us.

The high-side will continue to discharge only when the low-side gate starts to conduct.

BR

  • 0
    TI__Mastermind 23356 points

    Hey Tommy,

    What is your Vdrain voltage?

    The HS gate voltage seems to be measured with ground in your waveform. So the first dip is the gate turning off as the gate comes down from being 10-12V above SHx to the SHx voltage. Then there will be the deadtime between HS off and LS turning on to prevent shoot through.

    Is there any issue when operating the device?

    Best,
    Akshay