MCT8316A: VM up before 3V3 results in NACK on I2C Bus

Joel Gaudreault

Part Number: MCT8316A

Tool/software:

I use a Brushless 25 Click dev board from Mikroe connected to an STM32 Nucleo F103RB board. The 3.3V rail is regulated on the Nucleo board which is supplied by my laptop. The 24V VM rail is supplied with an external power supply.

Case #1: Power Nucleo and then VM; I am able to setup the MCT's registers through I2C and make my connected BLDC motor spin using PWM speed control. No issues found.
Case #2: Power VM and then the Nucleo; The MCT8316A returns NACK on the I2C BUS.

I originally thought the MCT8316A was stuck in sleep mode (no I2C) but I have modified my code to toggle the pin SPEED pin before talking to the MCT8316A and it still responds NACKs. I also tried manually pulling the SPEED pin high with the same result.

I don't see any references of a Power on Sequence in the MCT8316A datasheet. What am I missing?

Note: The PCB I am designing will use the 24VDC to supply downstream regulators (3.3V) so my VM rail will always be up before the 3.3V rail, which fits Case #2.

Thanks,

7 months ago

0 Venkatadri Shantaram84961 7 months ago

TI__Mastermind 23662 points

Hi Joel,

Can you provide full schematic, I am mainly looking for how pins FG, nFAULT, DRVOFF are powered?

If FG is low while powering up device I2C will not work, can you confirm.

Thanks and Best Regards

Venkatadri S

0 Joel Gaudreault 7 months ago in reply to Venkatadri Shantaram84961

Prodigy 20 points

Hi Venkatadri,

This is the full schematic, https://download.mikroe.com/documents/add-on-boards/click/brushless-25-click/Brushless_25_click_v101_Schematic.pdf

I have modified my brushless 25 click board so R7 is connected to AVDD instead of the 3.3V rail. It fixed the issue experienced in Case #2. I will have to do a rework on my boards coming out of the fab...

When you say: "If FG is low while powering up device I2C will not work, can you confirm", it seems like a bug more than an expected behaviour to me. Please note that figure 9-1 of the datasheet states that the FG and nFAULT signals can be pulled to an external supply when in reality, this is wrong. They should only be pulled to AVDD. This should be updated.

Venkatadri Shantaram84961 Please let me know if there are other hidden bugs like this and thank you for your help!

Cheers,

Joël

0 Venkatadri Shantaram84961 7 months ago in reply to Joel Gaudreault

TI__Mastermind 23662 points

Hi Joel,

Thanks for confirmation.

We will provide hardware FAQ soon , the FG pin is open drain and design recommendation to keep pull up always.

Thanks and Best Regards

Venkatadri S

0 Joel Gaudreault 7 months ago in reply to Venkatadri Shantaram84961

Prodigy 20 points

Hi Venkatadri,

Still, it does not make sense to me that an open drain output pin would have any impact on the power on sequence of the device. At worst, it should only compromise the function of the FG pin, not disable the whole I2C bus (which btw is pulled to an external rail and works fine??). I guess this is a specificity of your chip design.

FAQ are more of an optional document reference. Datasheets are what designers are referencing when implementing a chip in their design. Please make this FG pin PU requirement mandatory in your Datasheet and not a design recommendation. Otherwise, other designer might miss it.

Thanks,

0 Venkatadri Shantaram84961 7 months ago in reply to Joel Gaudreault

TI__Mastermind 23662 points

Hi Joel,

We will update to the data sheet in the next revision, FAQ is for quick information until datasheet gets updated.

FG pin is also used for other purpose which changes I2C mode and hence we recommend FG to be pulled high.

Thanks and Best Regards

Venkatadri S

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MCT8316A: VM up before 3V3 results in NACK on I2C Bus