Tool/software:
This is a new thread extending DRV8329: nFault condition on Startup
Based on your first waveform it seems that there is GVDD UV. Is the GVDD cap adequately sized and placed close to the driver GVDD pin?Yeah I was looking at the fault table and was pretty sure it was GVDD UV since it wasn't coming up. GVDD Cap is 10µF, the trace is very short through a via to the other side, the side of the cap is where we are measuring, you can see the GND connection to the cap is directly below the ground pad of the chip. there should be very little loop here.
Can you test with 20V PVDD? GVDD is generated from CP below 18V and from an LDO above 18V.
Yes i am using a power supply here is a waveform of the PVDD going to 21V and the GVDD gives up at around 10V
Also note when DRVOFF being pulled high causes nfault to be pulled low, this is an expected behavior from the device. So I would remove this variable when testing.
Yep, this can be fine for that split second, I have a hardware safety timer of sorts, that constantly needs to be toggled once every 1mS to maintain the DRVOFF low, the short high period is due to the fact that this circuit is does not run until the accessory +3v3_SW is turned on, prior to that, the DRVOFF is in that midpoint, This should only be an issue if DRVOFF turned off the GVDD generation, which if I read the datasheet right is not the case.
Also what is nsleep doing during this time?
nSleep is tied to PVDD at the moment, I had it controlled by an MCU pin, but since the MCU is powered by the AVDD of this chip, the circular logic of you need AVDD to get nSleep high but you need nSleep high to get AVDD didn't work, so i modified it. is it required that this be a pullup, not a direct tie to PVDD?
Below is the relevant schematic for reference:
