Tool/software:
Hi team,
My customer is using OCP auto-retry function of DRV8889-Q1. They want to know whether there is risk when DRV8889 keeps retrying every 4ms under overcurrent condition for 1 minute. They are worried it may cause heat accumulating and damage device, especially under high Tamb, like higher than 100C. From my understanding, the device has thermal shutdown function, so there's no risk here. Could you share some comments?
Best Regards
Grey
Hi Grey,
Thank you for your question. In OCP retry mode OCP_MODE = 1 b the retry is automatically 4 ms typical. This tine is sufficient to mitigate hot spot effect due to continuous overcurrent situation. When a OCP happens it means there was an abnormal condition. Once an OCP is detected customer must not re-enable the device until the cause for OCP is understood. This would be good design practice.
However, if the customer for the specific application wants to do the retry mode for a several time, as you mentioned the device has both Overtemperature Warning (OTW), and Thermal Shutdown (OTSD) protection.
If the die temperature exceeds the trip point of the overtemperature warning (TOTW), the OTW and TF bits are set in the SPI register. The device performs no additional action and continues to function. When the die temperature falls below the hysteresis point (THYS_OTW) of the overtemperature warning, the OTW and TF bits clear automatically. The OTW bit can also be configured to report on the nFAULT pin, and set the FAULT bit in the device, by setting the TW_REP bit to 1b through the SPI registers. The charge pump remains active during this condition.
If the die temperature exceeds the thermal shutdown limit (TOTSD) all MOSFETs in the H-bridge are disabled, and the nFAULT pin is driven low. The charge pump is disabled in this condition. In addition, the FAULT, TF and OTS bits are latched high. This protection feature cannot be disabled. The overtemperature protection can operate in two different modes: latched shutdown and automatic recovery. 7.3.11.6.1 Latched Shutdown (OTSD_MODE = 0b) In this mode, after a OTSD event all the outputs are disabled and the nFAULT pin is driven low. The FAULT, TF and OTS bits are latched high in the SPI register. Normal operation resumes after sending a CLR_FLT command, or an nSLEEP reset pulse or a power cycling.
This mode is the default mode for a OTSD event. 7.3.11.6.2 Automatic Recovery (OTSD_MODE = 1b) In this mode, after a OTSD event all the outputs are disabled and the nFAULT pin is driven low. The FAULT, TF and OTS bits are latched high in the SPI register. Normal operation resumes (motor-driver operation starts, nFAULT line released and FAULT bit goes low) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TOTSD – THYS_OTSD). The TF and OTS bits remains latched high indicating that a thermal event occurred until a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse.
Please see the device operation conditions under high temperature:
As explained above, the best practice is to check the root cause of OCP and then re enable the device. However, they can check the OTW and TF bits as a indicator for temperature rises in the device.
Please let me know if you have any more questions.
Best regards,
Mojtaba.
