DRV8350: GLA short to ground in high duty cycle and larger Cgs

Hi Team,

add failure process

1. INA produce extremely high/low duty cycle, very short falling edge

2.Once the gate pull down for 100nS, INA is turning to falling edge from the high signal, they see a up voltage spike.

3.About 300nS, gate have another up voltage spike, and VGLS pull down to 2.5V and driver reports fault

4.they test the driver pin, they found the low FET is short to ground

they think is because the upper FET and lower FET open simultaneously in output driver stage and cause this failure.

Yellow: Phase voltage, blue:GLA, RED: VGLS

Yellow: INA, Blue:GLA

Could you please check this urgent issue and give customer some feedback?

Thank you,

Yishan Chen

Hi Yishan,

What we think is happening is that there may be an abs max/min violation occurring on GLx due to not providing enough time for the low side gate to fully turn off before another "on" command is issued for the low side gate.

Since the duty cycle is so low, the voltage from GLx to SLx is not able to fully reach 0V before another command to turn on GLx is issued. We believe that this is causing the damage, as there is still sink current present due to the inductance of the trace when a new command is issued to turn on GLx again. The Cgs capacitance value increases the amount of time it takes for the GLx voltage to reach 0V, thus increasing the minimum duty cycle % necessary to achieve valid high side turn on.

So for the customer: Please ask them to probe the AT the GLA pin on the device and repeat the measurement. We want to measure voltage of GLA at device pin, not close to the MOSFET. Please also put the ground of the probe at the ground of the device. We believe if measured close to the device pin that we might see a higher voltage spike which could be damaging the device.

What is the lowest duty cycle % input where the high side is is actually able to turn on? The high side input command must be long enough to provide enough time for low side to turn completely off and high side to turn on. Due to this, the control software should not allow sending duty cycle inputs to high side that are below the minimum duty cycle % where the high side actually turns on.

The same is true for the low side. The customer should make sure that at high duty cycle %, make sure the low side has enough time to actually turn on. 

Thank you,

Joseph

To be clear on the waveform requested, could the customer please provide GLx, INHx, VGLS together to help us validate our theory. 

Thank you,

Joseph

Hi Joseph,

Please check below update waveform, measuring in the device pin.

Yellow: INA, RED: GLA MOS side BLUE:GLA device side

Thank you,

Yishan Chen

Hi Yishan,

Thank you for providing the waveforms.

I would like to ask about when the issue appears:

1. Will the customer ever see the issue during normal device operating conditions? 

2. Does the issue appear only during testing conditions, when providing very short pulse to INA?

Hi Jospeh,

This will happened only in short-duty cycle.

In customer control algorithm, they didn't limit the minimum duty cycle. So you can consider this issue will happened in customer 'normal condition'

Do you have any insight to solve this issue?

For example, increase the trace width, add some external component?

thank you,

Yishan Chen

Hi Yishan,

I understand. 

Here is some hardware modifications that could be tried to solve the issue:

1. Increase trace width. I don't know what the customer's current trace width is but making wider traces could help the issue.

2. I know you mentioned customer tested Cgs 4.7nF to 10nF. And issue was more probable at 10 nF.  Did they try using Cgs below 4.7nF? Maybe a smaller Cgs value could solve the issue. Customer can test different values below 4.7nF and see if their results are better.

If hardware modifications do not solve the issue, then I suggest a software limit for the minimum duty cycle to ensure correct operation.

Thank you,

Joseph

Hi Joseph,

Thank you for your answer.

But As we can see from the waveform that test GLA near the device, there are not voltage violation of low side gate output pin.

So, what is the root cause caused damage here?

Thank you,

Yishan Chen