DRV8428: M0/M1/VREF pin specifications

Hi Takanori-san, 

Thank you for posting in this forum. 

Takanori Kikuchi said:

1. If the FPGA IO drive capacity is 20mA, is it possible to control (H/L/Hi-Z) the M0/M1 pins of 30 drivers with one FPGA IO pin?
M0/M1 will not be changed frequently.
I would like to know the specifications required for this study.

As explained in section 6.5 Electrical Characteristics of DRV8428 datasheet can be accessible here : datasheet

each of the M0 and M1 output pull up current is 10uA. for 30 devices you need at least 600 uA.

Takanori Kikuchi said:

2. I would like to know the specifications required to supply to the VREF pin.
I am considering whether it is possible to supply VREF of 30 drivers from one DAC

The current regulation set point is adjusted by the voltage at the VREF pin. The Vref is utilized to set the full-scale current for the drivers based on the Kv: Transimpedance gain by  IFS (A) = VREF (V) / KV (V/A) 

As long as all devices have the same full-scale settings, it is fine use the same DAC for the drivers. 

The full-scale output current may need to be changed between many different values, depending on motor speed and loading. The voltage of the VREF pin can be adjusted in the system to change the full-scale current. In this mode of operation, as the DAC voltage increases, the full-scale regulation current increases as well. For proper operation, the output of the DAC should not rise above 3 V. Based on the bench test results the Vref current is about 20uA for each device. 

The VREF pin can also be adjusted using a PWM signal and low-pass filter.

Please let me know if you have any more questions. 

Best regards

Mojtaba.