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DRV8353RH-EVM: nFAULT have 20us pull low, which protection is it?

Sky Hsieh
Prodigy 40 points
Part Number: DRV8353RH-EVM
Other Parts Discussed in Thread: CSD19532Q5B

Tool/software:

Hi TI,

I use DRV8353RH-EVM to drive motor and I only modify MODE on EVM (connect MODE to GND and set 6x PWM mode).

When I drive motor with heavy loading, I find a 20us pull low signal on nFAULT pin every 3~10 second.

I won't find this condition on light loading.

I can't find any protection which will pull low for 20us in datasheet.

Please refer to the waveform below.

C1: DC Bus, C2: nFAULT, C4: motor phase current

  • 0
    TI__Expert 4375 points

    Hello,

    I agree it is abnormal to see nFault pulled low for 20us on this device. I would expect 8ms since you are using the hardware version.

    From what it looks like, it just reports the fault then clears it without affecting the device operation. Is this correct? Or when the nFault is low does it have any effect on output?

    Maybe this is a thermal protection being triggered? Have you checked the temperature of the device while seeing this condition?

    Thank you,

    Joseph

  • 0 in reply to Joseph Ferri
    Prodigy 40 points

    Hi Joseph,

    When nFAULT pulled low for 20us, I can hear that the motor have a little knock noise.

    I think PWM output also stop at the same time.

    I use a fan to cool down the temperature of EVM, the temperature of MOSFET is under 60 degree C. I think IC have not reach thermal protection yet.

  • 0 in reply to Sky Hsieh
    TI__Expert 4375 points

    Hello,

    I understand, thank you for the information.

    Would you be able to provide more waveforms so I can debug this further?

    Here is what I would like to check to see if everything is normal:

    Waveform with INA, GLA, SHA, and nFAULT at the time that the fault occurs.

    Thank you,

    Joseph

  • 0 in reply to Joseph Ferri
    Prodigy 40 points

    Hi Joseph,

    Sorry to have kept you waiting so long.

    Please refer to the waveform below.

    C1: nFAULT, C2: INLA, C3: GLA, C4: SHA

    pic.1

    C1: nFAULT, C2: INHA, C3: GHA, C4: SHA

     pic.2

    Please let me know if you have other waveforms you would like to see.

  • 0 in reply to Sky Hsieh
    TI__Expert 4375 points

    Hi Sky,

    Thank you for sharing the waveforms.

    I'm thinking this is might be a VDS fault since you mention it occurs at high loading. 

    Is it possible for you to change the resistor to set VDS pin to configure for higher VDS value?

    I would like to see if the issue still happens after this change.

    Thank you,

    Joseph

  • 0 in reply to Joseph Ferri
    Prodigy 40 points

    Hi Joseph,

    I only change Rshunt from 0.007 to 0.0035 ohm on EVM, and use fan for cooling to increase the power.

    When nFAULT is pulled-low, only the waveform of Vgsh of B phase is abnormal.

    VgslA/B/C and VglA/C are normal.

    C1: nFAULT, C2: Vgsl, C3: Vgsh, C4: Iphase

     (ZOOM IN)

     

    Then I add a 1000pF on GS side of six MOSFETs, loading can be increased about 20% .

    Then I increase VDS_OCP from 0.2V to 0.4V, the 20us FAULT does not show again.

    It seems the VDS_OCP has been triggered, but I have two questions.

    1. According to the waveform below, Vds is only 0.11V and which is far from 0.2V.

    Is it possible to trigger the VDS_OCP?

    Vds = 27.6A (C4: Iphase_peak) x 4mohm (CSD19532Q5B Rdson) = 0.1104V

    C1: nFAULT, C2: Vgsl, C3: Vgsh, C4: Iphase

    2. If VDS_OCP has been triggered, why the pull-low time period is 20us instead of 8ms?

  • +1 in reply to Sky Hsieh
    TI__Expert 4375 points

    Hi Sky,

    Thank you for all the effort. 

    1. This behavior makes sense. The RDSon value changes in relation to temperature. As the MOSFET heats up the RDSon value will increase which is why you cannot keep 4mohm as a constant value in this equation, and is also the reason why the VDS_OCP is being triggered

    2. The reason why it lasts 20us is because according to datasheet section 8.3.6.3: 

    "The MOSFET VDS overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be disabled on SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising edge on the PWM inputs will clear an existing overcurrent fault."

    So as you can see from your waveforms, the new rising edge on the PWM input clears the fault. They line up directly

    Thank you,

    Joseph

  • 0 in reply to Joseph Ferri
    Prodigy 40 points

    Hi Joseph,

    Thanks for your answer for question 1.

    Regarding answer of question 2, the PWM period is 50us, why nFAULT does not recover at next high side turn on? And why high side turn on shortly for 8 times before nFAULT pull low?

  • +1 in reply to Sky Hsieh
    TI__Expert 4375 points

    Hi Sky,

    nFAULT recovers at next pwm input rising edge either high or low side turn on. 

    I am not sure about the behavior of these pulses here. It is hard to tell without seeing inputs at this time as well.

    You are using the GUI in order to control EVM? Or are you providing your own signals from external MCU?

    Thank you,

    Joseph

  • 0 in reply to Joseph Ferri
    Prodigy 40 points

    Hi Joseph,

    I use external MCU to receive and provide signals to DRV8353RH-EVM.