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DRV8889-Q1: Questions about DRV8889-Q1

Part Number: DRV8889-Q1

Tool/software:

SPI is currently set to mode 1, that is, CPOL is 0, CPHA is 1, what is the communication frequency range of SPI?

The measurement of the FAULT foot has always been low level, may I ask whether the foot has always been low level can be eliminated through software control?

After the gui_loop is initialized, it enters the GUI_loop. If it is not possible to wake up the chip by gui_loop, what should I do

  • Hi Songhao,

    Thanks for your post.

    SPI is currently set to mode 1, that is, CPOL is 0, CPHA is 1, what is the communication frequency range of SPI?

    As per datasheet it can be up to 10 MHz SCLK. Typically applications use 1 or 2 MHz SCLK to minimize effects due to stray capacitances and glitches. 

    The measurement of the FAULT foot has always been low level, may I ask whether the foot has always been low level can be eliminated through software control?

    Are you referring to the nFAULT pin being active LOW? Please elaborate the use case. 

    After the gui_loop is initialized, it enters the GUI_loop. If it is not possible to wake up the chip by gui_loop, what should I do

    Sorry we do not understand what gui_loop means please explain? Did you mean the EVM-GUI app program? Which chip needs to wake up? Thank you.

    Regards, Murugavel