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DRV8353F:   DRV8353F:DRV8353F: SPI Register Write Issue

Part Number: DRV8353F

Tool/software:

Subject: Register Write Issue (ADDR2/5/6)

Hi all, reopening this thread with a clearer description:

  1. Normal Behavior

    • ADDR2 = 0x400 writes successfully.

  2. Issue Observed

    • During incorrect operation, ADDR5 and ADDR6 unexpectedly accept 0x400 (not my target value).

    • But writing the correct 

  3. Key Questions

    • Root cause? (e.g., address mapping conflict, clock sync, write protection?)

    • Any required pre-write sequence?

      ADDR2 write 0x400  correct 



      ADDR5 write 0x12D fail   (default 0x16d)


      ADDR5 write 0x400 successfully
  • Hello,

    Regarding the root cause:

    I know you mentioned you checked to make sure the bits did not put the register in a locked state, so I don't think that is the issue.

    There is also no pre-write sequence that is needed.

    Can you elaborate on what you meant when you said:

    • "ADDR2 can be written (e.g., 0x400, 0x410, 0x420), but continuous writing is not possible—the operation must be disabled first."

    Also, please make sure you are following the SPI timing diagram outlined in the datasheet

    Making sure to sample on falling clock edge (CPOL and CPHA settings in your code)

    Thanks,

    Joseph

  • Hi all, refocusing the issue:

    Observations

    ADDR5 accepts incorrect values (e.g., 0x400)

    Fails when writing correct parameters

    Context

    ADDR2 works normally (proof of basic write function)

    Core issue is ADDR5

  • Hello,

    The biggest possibility to me is 0x12D write having much more switching on the SDI line than the 0x400 write. 

    Some questions:

    1. How long are the SPI lines on your board? I see that there is some ringing present on your SPI lines, so this leads me to question the timing/integrity as a whole.

    What else could be the explanation for some writes working and some not? It's clearly not an issue with your formatting, as it is able to perform successful operations.

    2. Please provide a zoomed in scope on only the unsuccessful write transaction for further analysis. 

    Thanks,

    Joseph