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Original question:

DRV8912-Q1: SPI Messaging for Large DRV89xx Chain

DRV8904-Q1: Clarification on SPI Daisy Chain Response Format – DRV8904-Q1

Software Signal
Prodigy 20 points
Part Number: DRV8904-Q1

Hello,

I'm working with two DRV8904-Q1 devices in a daisy chain configuration and I'm trying to fully understand the SPI response format, particularly during write operations.

According to section 8.5.3.1 of the datasheet, the SPI response after a write command should include:

  1. 2 bytes of status (one per device, in reverse order),
  2. 2 bytes echoing the header,
  3. 2 bytes containing the previous content of the register that was written.

However, in my tests, the last 2 bytes of the response always match the register address I just wrote to, not the previous content of that register. For example, when writing to register 0x07, I consistently receive 0x07 0x07 in the last two bytes of the response, regardless of what value I write.

I also tested with register 0x1F and received 0x1F 0x1F, which further suggests that the response contains the address, not the previous value.

Could you please clarify:

  • What exactly is returned in the last 2 bytes of the SPI response after a write command in daisy chain mode?
  • Is the datasheet incorrect or incomplete in this regard?

Thank you in advance for your help!

Best regards,

Paolo Coita

Signal s.r.l. - Italy

  • 0
    TI__Mastermind 44145 points

    Hi Paolo,

    Thank you for posting your question in this forum. The datasheet description is correct. It shows an example with 3 devices in the daisy chain. See this application note as well. And this code 

    Software Signal said:

    According to section 8.5.3.1 of the datasheet, the SPI response after a write command should include:

    1. 2 bytes of status (one per device, in reverse order),
    2. 2 bytes echoing the header,
    3. 2 bytes containing the previous content of the register that was written.

    This is correct. See below snippet showing expected responses. The last two bytes would be previous contents of the registers that was written with R1 being the last byte. This daisy chain is implemented in several of our SPI devices including the DRV8904-Q1 family of devices and in use in several applications. 

    See the attached pdf for example code implementation showing N = 4 daisy chain which can be adapted for N = 2.

    3733.Daisy Chain SPI with Motor Drivers.pdf

    Could you please verify the hardware connections as well as share the SPI captures for example with a Saleae SPI sniffer? Need simultaneous captures of nSCS, SCLK, SDI1, SDO1, SDO2 for debug. Thank you.

    Regards, Murugavel  

  • 0 in reply to Murugavel4637
    Prodigy 20 points

    Hi Murugavel,

    first of all thank you for your promptness.

    Your suggestion to check SPI lines with an analizer helped me to discover the issue: the problem was that low level SPI library swaps the bytes couple by couple, so what was actually going out on SDI1 was

    80 82 etc.

    instead of 

    82 80 etc.

    After having fixed this behaviour, eveything is working as expected.

    Kind regards,

    Paolo C.