Other Parts Discussed in Thread: CSD19532Q5B
Tool/software:
Hi,
We are currently evaluating a BLDC motor driver design using the DRV8353RS. We would like to ask for your input regarding the gate drive current settings, specifically related to the Gate Drive HS and LS registers (addresses 03h and 04h).
In our evaluation, we observed that using the default register settings after power-up (HS = 1000mA, LS = 2000mA) worked fine on the TI evaluation board. However, on our first prototype board, the motor exhibited unstable behavior under the same conditions.
After investigating, we found that reducing the Gate Drive HS/LS settings to 100mA / 200mA resolved the issue. Further analysis showed that the external FET we are using (CSD19532Q5B) has a typical gate charge (Qg) of 8.7nC, and based on that, the required gate current for a switching time of 100–300ns is estimated to be around 30–87mA. Therefore, we believe that settings such as 50mA / 100mA are within the appropriate range.
For detailed waveform information, please see the PDF below.
Custom PCB Waveform Information.pdf
While our testing supports this adjustment, we would appreciate your feedback on the following points:
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When using a FET such as the CSD19532Q5B (Qg = 8.7nC), is it generally acceptable to configure Gate Drive HS/LS currents to approximately 50–100mA, assuming a target rise/fall time of 100–300ns?
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If the drive current is reduced too much, what kind of adverse effects (e.g., increased switching loss, risk of shoot-through, etc.) should we be cautious of?
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The dead time is currently set to the default value of 400ns provided by the TI example software. Given the Smart Gate Drive features such as VGS handshake and automatic minimum dead-time insertion, is it safe to assume that no adjustment to the dead time is needed even when the gate current is reduced?
Best regards,
Conor
