DRV8106-Q1: Fault pin and status register are out of sync

Vishnudas N Kartha

Part Number: DRV8106-Q1

Tool/software:

Hi,

I have configured the UVOV_CTRL register with the value 0xF4. With this setting, I observed that the FAULT pin is asserted when the power supply voltage exceeds 28.5 V. However, the corresponding fault bit in the status register does not indicate this condition.

As per my understanding, setting 0xF4 should disable the PVDD supply overvoltage monitor mode. Given that, I’m unable to understand why the FAULT pin is still responding to voltages above 28.5 V.

Could you please help me understand this behavior?

Thank you for your support.

Best regards,

Kartha

3 months ago

0 Shinya Morita 3 months ago

TI__Mastermind 45145 points

Hi Thank you for your questions. Will feedback to you in a day or two.

0 Shinya Morita 3 months ago in reply to Shinya Morita

TI__Mastermind 45145 points

Hi,

Thank you for your questions.

If PVDD_OV is disabled by SPI, DRV will not make nFAULT pin low because of PVDD_OV.

- May have other fault is happening.

-Or PVDD_OV was not disabled by SPI in some reason.

Thanks,

Could you generate new post if you have further questions.

regards

Shinya

0 Vishnudas N Kartha 3 months ago in reply to Shinya Morita

Prodigy 40 points

Hi,

There are no other faults, and the over voltage fault is not enabled in any means.

I have read the register multiple times and can see no bits are set. And i noticed one more thing that, the fault pin is de asserted after few seconds.

I don't know why this is happening.

Thanks.

0 Shinya Morita 2 months ago in reply to Vishnudas N Kartha

TI__Mastermind 45145 points

Hi,

Thank you for the update. If no fault is detected, nFAULT should not go low.

regards

Shinya Morita

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DRV8106-Q1: Fault pin and status register are out of sync