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DRV8353R: Low-Side Gate Driver Loop Layout

Part Number: DRV8353R


Tool/software:

Hi TI,

I found the low-side gate driver layout guideline in datasheet, which says I should minimize the loop from GLx -> LS gate -> LS source -> SPx.

Also the layout guidelines of motor driver says: 1. Use thick trace for gate (at least 20 mil). 2. Use kelvin connection/differential pairs for current sense signals.

According to the guidelines above, I would like to know which approach is better.

Regarding GLx:

Use at least 20 mil trace and beside SPx trace.

Use at least 20 mil trace but a different layer overlap with SPx trace.

Regarding SPx:

Use 10 mil and differential pairs with 10 mil SNx.

Use 20 mil and differential pairs with 10 mil SNx.

Use 20 mil and differential pairs with 20 mil SNx.