DRV8873-Q1: DRV8873HPWPRQ1

Hi Darsana,

Thanks for your post.

Darsana S said:

1.Could you provide the equation for finding bulk capacitor value in the application of DRV8873 motor driver used to drive solenoidal valve (32V ,2A )?

As mentioned in TI forum related thread, it's recommended to use 4uF/W, so we proceeded with value of 220uF for our application.

Although this was meant for a BDC motor, this application report applies to inductive loads including solenoids. It shows calculations. Also, this video will be informative.

Darsana S said:

Even after placing this bulk capacitor , we are observing the huge spikes for some microseconds of amplitude 28V at output1 & output 2 of the DRV8873 motor driver.

3. Same kinda spikes were observed at the evaluation board also at OUT1 & OUT2.

This could be because of high inductance of the solenoid load in your application. I assume the drive is bidirectional for this solenoid. Could you please share the voltage waveforms at OUT1 and OUT2 ? If using PWM to drive please include zoomed waveform to show 2 to 3 PWM switching cycles? What is the VM voltage used in the application? See below absolute maximum specifications for OUT1 & 2. Spikes < 1 V higher than VM and lower than GND on OUT1 & 2 are okay. If it exceeds this specification it could damage the device and must be mitigated. 

Using four Schottky diodes in parallel with each of the output FETs body diodes between VM to OUT1 and OUT2 and OUT1 and OUT2 to GND will reduce this spike which is due to high inductance of the solenoid. Increasing VM bulk capacitor will not resolve the inductive spikes.   

Regards, Murugavel 

Hi Darsana,

Please clarify - how is the load connected and driven, the sequence of this operation. Why were you using a resistive load? If current regulation is setup and required for the application it will not work with a resistive load. To simulate a BDC motor you must use a resistor and inductor in series, for example 10 Ω and 1.5 mH in series as a test load.

Darsana S said:

The chip is configured in the hardware PWM mode and driving the OUT1 and OUT2 with 600 ms time gapFigure2

See below control table from the datasheet for PWM mode drive control. The default inputs in this mode must be logic high on IN1 and IN2. For driving with PWM input 0 to 100 % duty cycle, depending on the direction needed one of the INx must be logic high and the other INx must be PWM input. The drive time would be during PWM off, inverse logic. This is the suggested control scheme with PWM input. For full drive (100 % speed) the driving INx will be 0 - logic low. If you follow these and use R and L as load for current regulation there should be no issues. 

Regards, Murugavel