DRV8316: Delay Compensation at Current Zero Crossing

Hi Dominik,

Thank you for the detailed explanation and testing.

So, when setting DLY_TARGET for 1.2us, what is the exact "delay time" that you observe? I can't tell from the scope shot, but it looks like the delay behavior looks correct.

I'm wondering if you're certain that the voltage dip you see at the zero crossing is due to this 2.3% error in OUTx duty cycle. To me it looks like the voltage dip you see in the initial waveform looks like it was caused by something more significant than the duty cycle error.

I'm also interested in the fact that the issue disappears at 20kHz. Were you able to test at any intermediate PWM values between 20 and 100 and see if the issue gradually reduces, or if it is present completely until ~20kHz.

Let me know your thoughts.

Thanks,

Joseph

Hello Joseph,

and thank you for your reply. I will be able to do measurements again next week.

I will add screenshots to verify the exact delay between input and output PWM. I think that the delay target was met relatively well at first glance. At first I was also suspicios whether maybe some PWM cycles are missing or the supply voltage dips but this is not the case. You can see from this persistance shot for example, that there are no very short or missing pulses due to an overcurrent situation or similar, and you can also see a jitter in the delay of the rising edge (CH2 INHA, CH3 OUTA):

However, the sinus that I am running as a test only has an amplitude of 4% duty cycle (notice the range in the persistance view). This means that even small distortions lead to significant changes in the voltage. We noticed that, because a 0A setpoint in our motor controller is a valid operating point and it becomes noisy at high PWM frequencies.

I also previously tested some intermediate frequencies. I do not think that it is a binary effect but that it becomes less and less noticeable. Maybe it was also ok in the 40kHz range already but it gets harder to tell because the current ripple also increases.

To me it feels like the delay compensation feature is only precise to a certain constant limit/quantization. And this becomes more relevant as the periods get shorter. Notice that the 100ns range jitter that was mentioned in the related thread would already be 1% duty cycle at 100kHz. So some timing effects in this range seem realistic.

Regards,

Dominik

Hi Dominik,

Thanks for the update. Yes I can see that there are no missing/short pulses.

I think you are correct that the compensation becomes less precise as your frequency increases and period shortens. This makes sense to me. However, what is confusing me now is that you see the "expected" ~1% error before and after the distortion, and the motor current is fine.

To me, this looks like a behavior that is unique to a phenomenon which is only happening at the zero crossing for some reason. If the delay behavior is normal both before and after the distortion at zero, what would cause the DLY_TARGET change for this value only and be the culprit here? 

I can check with the team internally and see if this is a known issue, but to me it seems like the issue is coming from elsewhere.

Please let me know if my understanding here is wrong.

Thank you,

Joseph

Hi Joseph,

I think that the 1% offset is not relevant as long as all channels behave the same. The motor only experiences the voltage difference.

Concerning the behavior during zero crossing of the current, the literature knows the "zero current clamping distortion" effect, so it seems plausible to me that there is something different happening during that time. I would happily hear from the engineering departement about the observed behavior.

I also did some more measurements and changed around the setup a bit so that the effects can be better isolated. The measured channel A is held steady at the center of the sinus which is still running on channel B while channel C is disconnected:

Again current (CH1) and low passed voltage (CH4) at phase A:

Now for the measurements of the effective delay that you requested (still configured to 1,2us).

Good case (1.18us rising, 1.15us falling edge):

Bad case (1.06us rising, 0.99us falling edge):

Now to check again for stable 50% duty cycle at the input, and varying duty cycle at the output with a persistance view:

Varying delay for the rising edge:

And for the falling edge:

And now for the same setup but with 20kHz instead of 100kHz:

With persistance view:

So I would say that the precision of the delay compensation stays the same over the frequency range, its impact just grows for smaller periods. Also the effect at zero crossing still persists, it just gets less noticeable relatively, and negligible for our use case.

Kind regards, Dominik

Hi Dominik,

Thanks again for the update. I think the persistence scope capture is a good depiction of what is happening here. 

I talked with the team and it is likely that this feature was targeted for operation around 20kHz as is typical for many of our devices, and the delay feature just gets progressively less accurate due to the shortening of the period as we thought.

As for the solution to the issue in regards to your system, is it possible to operate at ~20kHz? I'm not sure if this phenomenon is avoidable at higher PWM frequencies.

Best regards,

Joseph

Hi Joseph,

I think we have to evaluate for ourselves now, how we can deal with the behavior. For clarity's sake, in your opinion there is no SPI parameter that we missed which could remedy the distortion?

As there are some variants of motors to control, I now checked a motor with the following parameters:

• phase to phase resistance: 11.3Ohm
• phase to phase inductance: 98uH

The distortion in this case looks much better at 100kHz:

Now again for the experiment with phase A at 50%:

It looks like the jitter in the rising edge is improved, maybe also the amount of time that the signal is in the middle of the tolerance. Because the total waveforms look better - especially the current.

I guess that's it for now apart from the question about the SPI parameters.

Thank you for your support and kind regards, Dominik

Hi Dominik,

These are interesting results. Thank you for sharing using different motor parameters.

It is clear that the current is much more smooth and stable in this scenario.

To answer your SPI question, there are no other registers that I can see affecting/remedying this in any meaningful way.

Hopefully the device's performance is now acceptable for your operation.

Thank you,

Joseph