DRV8434A-Q1: HTSSOP package availability

Hi Rahil,

The DRV8434-Q1 has one fault indicator pin nFAULT for all the faults and an STL_REP pin for indicating a motor stall. 

Rahil said:

we understand this device lacks an SPI interface and utilizes a single fault output pin for all indications. Our objective is to precisely identify the specific fault type. 

Unfortunately it may not be straight forward to differentiate all possible faults based on the nFAULT pin status.

It may be possible to observe certain patterns and make a conclusion based on the that. See the Fault Condition Summary table in the datasheet. Because the stall detection has a dedicated report pin as well as nFAULT this can be easily differentiated. An open load OL would report on the nFAULT but the motor would continue to be driven with the other connected coil. If there was an OCP event the nFAULT would self clear after tRETRY and repeat pulsing if the over current, for example a STB short to battery and  STG short to GND event. tRETRY is a defined 4 ms repeat rate which may be used for differentiation. OCP will also disable the outputs and re-enable after tRETRY repeating this pattern until the short is removed.

VM UVLO, this is the only case where the indexer is disabled and resets when VM recovers. This would put the indexer back to HOME position 45 ° electrical angle. All other faults would keep the indexer operating. For example VCP CPUV fault would disable the output but keep the indexer operating which would show as missed steps if CPUV fault was intermittent. In practical use CPUV never happens unless the VCP pin was mistreated or device damaged. Lastly a thermal shutdown TSD. This would keep indexer operating but outputs disabled during such event and recovers when the device cools down. The effect of this would also be missed steps or position error.  

Rahil said:

Additionally, please confirm if the DRV8343A-Q1 is available in the HTSSOP package.

It is available in VQFN package option only. Thank you.

Regards, Murugavel 

Dear Murugavel, Thanks for the feedbacks.

"If there was an OCP event the nFAULT would self clear after tRETRY and repeat pulsing if the over current, for example a STB short to battery and  STG short to GND event. tRETRY is a defined 4 ms repeat rate which may be used for differentiation. OCP will also disable the outputs and re-enable after tRETRY repeating this pattern until the short is removed."

during my lab measurement i observed below behavior. as you explained every 4ms tRETRY kick in to check fault presents.

Our requirement is to identify fault(SCG/SCB) on coil1 and Coil2..

in datasheet mentioned any faults on outpins, both H-bridge will shut-off..

We want suggestion/solution from your-side to identify the individual fault on col1 and coil2.

Thanks

Rahil

Hi Rahil,

Rahil said:

Our requirement is to identify fault(SCG/SCB) on coil1 and Coil2..

in datasheet mentioned any faults on outpins, both H-bridge will shut-off..

We want suggestion/solution from your-side to identify the individual fault on col1 and coil2.

Unfortunately it is not possible to differentiate which coil A or B was shorted natively in this specific driver device. An SPI registers based driver such as the DRV8889-Q1 can provide such granular information via SPI registers. 

Regards, Murugavel 

Hi Murugavel,

Thanks for the suggestion.

DRV8889 has higher RDS so we didn't select the device.

can you please confirm below method will work.

In case of Fault pin output LOW due to fault; controller should disable the Driver by ENABLE/nSLEEP pin. then monitor the driver output pins confirming fault.

Thanks

Rahil. 

.

Hi Rahil,

Rahil said:

can you please confirm below method will work.

In case of Fault pin output LOW due to fault; controller should disable the Driver by ENABLE/nSLEEP pin. then monitor the driver output pins confirming fault.

This may be workable. The digital port pins could distinguish between logic low and high but not any intermediate voltages. When the bridge is active the voltages would be switching on and off for regulating the current via the coils. So logic levels would be pulsed at a rate of 20 to 80 kHz not a DC level. This must be considered. When nSLEEP = 1, the output voltage will no longer be switching and likely read 0 V assuming no SCB. 

Regards, Murugavel