Part Number: DRV8803
Hello to everyone,
I am currently designing a board utilizing the DRV8803 to drive power outputs. To minimize the microcontroller pin count, I am looking to use the bare minimum number of control lines.
I have already decided to leave nENBL unused (permanently enabled). Furthermore, I am considering omitting the nRESET pin. According to the datasheet, asserting nRESET (High) clears internal faults such as Overcurrent (OCP). In my specific application, the supply voltage (VM) is frequently cycled since the device performs a Power-On Reset (POR) whenever VM is applied, I intend to rely on this power cycle to clear any fault conditions.
Could you confirm if there are any hidden risks in leaving nRESET permanently tied to GND (inactive)? Specifically, are there any fault states that require a logic-level reset pulse which a VM power cycle would fail to clear?
Thank you
Best Regards,
Evangelos
