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DRV8412DDW

Manuel Palzer
Prodigy 20 points
Other Parts Discussed in Thread: DRV8412

Hello,

I have a problem with the DRV8412DDW.

Take a look on the datasheet page 20, figure 13. DRV8412 Schematic Example. You see the example like I have layout the DRV8412.

M1 is on a high-signal (3,3V), M2 and M3 are connected to Pin 12 (AGND).

On PWM_A and PWM_B are two PWM-signals which are phase-shift of 180°. GVDD = VDD = 12 V and PVDD = 24V.

PWM_C and PWM_D are disabled.

At each Output (Pin 29 and 31) I have +10VDC. This should be the problem, I anticipate a PWM-Signal too.

Thanks for your help,

Manuel

  • TI__Guru 55615 points

    Manuel,

    What are the /RESET signals doing?  They should be HIGH. 

    Is /FAULT or /OTW LOW....these signals should be pulled up to VREG with external resistor since they are open-drain outputs. 

    Is there a load connected?  If so, do you have OC_ADJ set appropriately for the rated load to not cause an OCP?

     

  • in reply to Ryan Kehr
    Prodigy 20 points

    Thanks for your help,

    but a few minutes ago I have resolved the problem. 

    The /Reset_AB was high and /Reset_CD low. /Fault low and /OTW high.

    I only use the bridge for signals A and B, therefore I have the Pins for signals C and D not connected. This was the failure.

    Now, where PVDD_CD, GVDD_CD are connected and between BST_C and OUT_C also BST_D and OUT_D were a capacitor the problem is solved and the Bridge-PWM-Driver is working correctly.

    Have a nice day and thanks for your answer.