DRV8301 Questions...

David,

1. Does EN_GATE (pin 16) have anything to do with SPI function?  (e.g. is SPI disabled while motor is running?)

 SPI is not disabled during motor operation.  However, you must wait a minimum of 5ms and max of 10ms AFTER EN_GATE transitions high to communicate with the device.  This is specified in the tabular data.

2. Do I understand correctly that if SCS (pin 8) is pulled low that SDO (pin 10) will immediately quit being in tri-state?

Correct.

3. Assuming VDD_SPI has power (5V) is there any condition which would prevent this?  (e.g. SCKL state)

Other than the delay mentioned in #1.   

4. If SCS/SDO action does not happen, is it a good presumption the IC has been damaged?  (even though other functions work?)

 Hard to say for sure, but assuming you have not over-stressed the device before attempting to communicate, then I doubt the IC is damaged. 

As implied by the questions, our main problem is deciding whether we have multiple damaged chips or a bad SPI setup.

One of the things we have as a backup is going to the DRV8302.  However, I don't understand how the slew control works on that chip.

5. Is there a write-up explaining slew control on DRV830x chips?

 When using the DRV8302, you could simply install series resistors with the gate drive to slow down the edges.  The gate drive current is maxed out to the highest setting as the default for 8302, so there is no way to adjust this.  We don't have a write-up other than the description in the register map for the DRV8301 where you can choose a lower level of gate current that will slow down the switching edges when charging the external capacitance in the FET.  I = C * dv/dt.

6. Does it matter if SP1, SN1, SP2 and SN2 are disconnected (floating)?

 No.  This doesn't matter at all. 

An existing code base does exist for the DRV8301-HC-C2-Kit.  You have to download "ControlSUITE" from ti.com to see the code.  This might be helpful to follow as a baseline for SPI programming.