• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 30 subscribers
  • Views 741 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Cycle-By-Cycle Current Limit of Three-Phase PWM Motor Driver (DRV8312/32)

Dan Xiao
Prodigy 110 points
Other Parts Discussed in Thread: DRV8312

Dear TI Application Engineers,

I have two questions about motor driver IC DRV8312/32 regarding the cycle-by-cycle current limit with high side OC (please refer to Fig. 6 in the datasheet).

1. Why does the device turn on the low side FET when high side OC is detected, as well as turn off the active high side FET carrying the current? what is the advantage of doing that instead of keeping the low side FET off?

2. If the high side FET is forced off and the low side FET forced on immediately and simultaneously at high side OC, there should be a hard short via the DC bus and this FET leg (see the falling and rising edges in the highlighted solid line in Fig. 6).

Best Regards,

Dan

  • 0
    TI__Prodigy 560 points

    Hi,

    1. when high side OC is detected ,it turn on the low side FET, so the current will decay slowly, if we keep the low side FET off , the current will decay fast, and the torque will ripple;

    2. the DRV8312/32 have a dead time between the high side FET off and low side FET on,  to prevent the shoot- through

  • 0 in reply to Brady Lin
    Prodigy 110 points

    Hi Brady,

    Thanks for your information.

    Regarding your first answer, when high side OC is detected, the load current must be in the positive direction (DC+ charging the load through the high side FET). Whether the low side FET turned on or not, the current will decay through the low side FET body diode (FET is kept off by the diode drop). Even though it affacted the decay speed, it should take the same action when low side OC is detected. But the drive turns both high and low side FETs off at low side OC.

    Regarding the second answer, the drive has the deadband generator after the cycle-by-cycle trip action (if I am right). In other words, edge delay can be added to the tripped complementary PWM waveforms, i.e. high side falling edge and low side rising edge at high side OC.

    I am looking forward to your earliest answer.

    Happy New Year!

    Dan