Hi,
I am working with a DRV8301 and I am a little confused by the datasheet description of the SPI. I am trying to read the status registers for a fault, and I know that the status registers clear when read.
On page 19 of the DRV8301 datasheet (the most recent one it appears), TI makes the following statement regarding reads:
"The MSB bit of SDI word (W0) is read/write bit. When W0 = 0, input data is a write command; when W0 = 1,
input data is a read command, and the register value will send out on the same word cycle from SDO from D10
to D0."
This statement seems to imply that the DRV8301 would send the status register in the same word cycle as when the SPI master issued the read of the status register.
However, the document also says: "For a read command (Nth cycle) in SPI, SP0 will send out data in the register with address in read command in
next cycle (N+1)."
Could someone please confirm which behavior is correct?
I am unsure if the read should come on the same word cycle. I am able to produce an overcurrent state by setting OC_ADJ to 0 in CR1, and I think I am getting a status register of 0 when the SPI master try to read it the word cycle after the status register read command. I got values of 1 and 4 from the DRV8301 in the same word cycle as the status register read command, which is more reasonable, but this could be from a previous command.
Jeremy
