DRV8432 Just doesn't work.....

Mike,

A few things that stand out or I am trying to understand. Do you have large decoupling caps on the GVDD and PVDD supplies? What is the purpose of R82/R83 to ISENSE lines? Are you intending to smooth the output with the capacitors (you are driving a DC motor correct)?

Hi Nicholas,

Yes there are large (well, 470uF 50V) electrolytic capacitors, positioned in the same place as on the evaluation board. The PVDD cap is physically close to the middle of the "right" side of the IC.

The capacitors on the motor outputs were to smooth them, as with the evaluation module, but I've tried the circuit without them too. The circuit behaves the same with or without them.

R82 and R83 simply go to ADCs  of our controlling processor for monitoring purposes. I've just cut the tracks to these resistors at the 0.05R sense resistors and it has made no difference.

The layout is attached too for reference. The highlighted section is PVDD.

Mike

Mike,

Have you tried monitoring PVDD and GVDD on a scope as you apply the PWM signal? Possibly trigger on nFAULT and get a scope shot of PVDD and GVDD. You could also monitor the current with a probe to see if it is spiking when you send the signal. This sort of error seems to lead to some sort of undervoltage or overcurrent problem when you enable the Full Bridges.

Mike,

Another note, in your layout it almost looks like pin 20 and 21 on the DRV8432 are shorting. This could possibly cause the issue you are seeing. Could you check this out.

Mike,

Try removing all of the capacitance after your inductor/bead.  If you look at the schematic in our EVM user guide, we list these as a stuff option for DC output.  If you are switching, you are most likely hitting an OC fault when charging these caps. 

http://www.ti.com/lit/ug/slou291a/slou291a.pdf

Figure 3, page 6.

Thanks Nicholas - they are not shorting.

Thanks Ryan - they are not fitted on this board.

Mike,

Let me know if it is possible to get some scope shots.

Hi Nicholas,

Sorry for the delay - I have been away on business and on holidays.

This capture shows GVDD (CH1 yellow) and PVDD (CH2 white) against the fault line output (CH3 purple).
What isn't shown is that the device is taken out of reset 200ns before the fault line activates, with a steady 10% 15kHz PWM signal being applied since power-up.

The incoming PVDD supply does dip from 24V to 18V, but the 12V GVDD derived from this is pretty good I think.

Is this PVDD dip enough to trigger a fault?

Thanks,

Mike

Hi Mike,

If I am reading the scope shot right it looks like there is about a 1V drop in GVDD right before nFAULT asserts This drop may actually be even worse if the GND is bouncing as well. Is this with no motor connected? That is pretty severe noise on PVDD.

There are no motors connected. I have just the inductors on the output lines, and a couple of contra-wired LEDs across the motor connector to indicate motor direction.

Would you agree that PVDD must be being pulled down by the DRV8432 itself, as it doesn't go anywhere else (other than the 12V supply).

It is possible that I have a faulty IC?

This is the second one I've tried, so I'd be surprised if both are faulty.

Hey Mike,

I am having the exact same trouble that you have described. Did you figure out a solution? I am quite desperate to figure this out myself. Else I will just have to replace my controller and see if that helps. I have replaced two drvs already and both show the same behaviour. I do not think that the IC is faulty. 

Rohit

Hi Rohit,

I had T.I. engineers look over my schematic, and the layout of my PCB in detail.

We analaysed it over a couple of weeks.

They could find nothing wrong with either.

In the end I gave up and used a different part (not from T.I.), which worked first time.

Sorry I can't be of more help. I'd advise you cut your losses and use a different manufacturer.

Thanks Mike. I appreciate your prompt reply. 

Hi Rohit,

Can you share some more details specifically about the issue you are seeing and how you have the device configured? I'd be happy to try and resolve it. We have this device designed into a variety of projects without issue. 

Things to see would be the schematic, layout, and scope plots of the event occuring (showing the input, output, nfault noctw, pvdd, and gvdd) would be a good first step.

I wonder if there's simply insufficient bulk capacitance on PVDD.  The EVM uses 1000uF, versus your 470uF.  With 10V of movement on the power rail shown in the waveform, I would try to make that stable first.

Best regards,
RE