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DRV8301: the timing diagram for EN_GATE vs. n-SCS

Jordda
Intellectual 665 points
Other Parts Discussed in Thread: DRV8301

Hi,

Just like to double confirm one thing for DRV8301 SPI. Please refer to the attached picture. Based on the datasheet, MCU cannot send any SPI command to DRV8301 successfully if T_SPI_RAEDY > 10 ms.  So the 2nd SPI cannot be sent to DRV8301 successfully. Is it true ??

Thanks for advice.

  • 0
    TI__Mastermind 21320 points

    Hi Jorja,

    EN_GATE low puts the device into a low power consumption mode in which SPI does not function. It takes 10 ms max for the device to be ready to receive SPI data after bringing EN_GATE high.

    So looking at your waveform, 3 ms should be 10 ms to allow for valid data transfer. There should be no issue with the 2nd SPI command if EN_GATE is staying high.

    Also, I believe there is a more recent version of the datasheet on the web. No major changes, just a few slight updates.