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Using RESET in conjunction with PWMA and PWMB for specific logic for DRV8412

Other Parts Discussed in Thread: DRV8412, LMD18200

Hey there team,

Is there a way to get a Logic Truth Table for DRV8412 to show how to use the RESET_AB in conjunction with PWMA and PWMB to match the operation with LMD18200?

I believe Rick had recommended that this could be done using mode 1 (wouldn't have been possible in mode 4).

As background:

First, he’ll choose the motor driver, then work on the MCU.

Replacing LMD18200 is on the table because they’ve been using the part for so long, and he thinks that replacing it with a newer generation part like DRV8412 would assist with the 20 year lifespan requirement, and DRV8412 is a dual channel in 1 part so there may be opportunity for integration – they currently use two LMD18200’s on 2 separate boards with 5 channels each to control 10 motions of their Pittman servo motor.

The motor is a DC Servo Motor, not doing any microstepping.

The engineer thinks that he may need to control his motor as 4 separate high side and low side drivers, but he’s not sure of the timing without the glue logic. I’ve ordered him a DRV8412 EVM to test so hopefully we’ll have some real feedback by the end of next week.

He knows he’ll need a general purpose MCU, something with a lot of timers (there are 10 motions to control), and encoding needs to be done in encoder as much as possible.

If he finds that the timing is getting too complicated, he may stick with the LMD18200 as a back-up.

Thanks for the quick response.

-John S

  • Hi John,

    Here is the table that should work. There are a few cautions.
    1) The table has not been checked out, although it appears to match both datasheets.
    2) The old saying about details comes into play here. While the table works, timing may not be optimal when entering and exiting reset.

    The first four columns is the LMD18200 truth table, and the last four is the DRV8412 equivalent. nRESET_AB is used to designate RESET_AB is active low.

    LMD18200 DRV8412
    PWM DIR BRAKE OUTPUTS PWM_A PWM_B nRESET_AB OUTPUTS
    H H L Source 1, Sink 2 H L H Source A, Sink B
    H L L Sink 1, Source 2 L H H Sink A, Source B
    L X L Source 1, Source 2 H H H Source A, Source B
    H H H Source 1, Source 2 H H H Source A, Source B
    H L H Sink 1, Sink 2 L L H Sink A, Sink B
    L X H NONE X X L

    NONE