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DRV8432 OTW FAULT VREF

ALbert Tello
Intellectual 735 points

We experiencing problems with drv8432 , is new design where we can look to find the mistake

Vref = 0 , only connection is M1, we follow  0.1uF and 1 Ohm between GND and ANGND

No motor is connected ,

OTW =0

FAULT=0

We reset Bridge_AB , Bridge_Cd

VDD=GVDD[A..D] =12 V

PVDD  =24V

Any suggestion to look where can be our mistake

Regards

Albert

 

IS

  • 0
    TI__Guru** 114905 points

    Hi Albert,

    I am assuming you mean VREG = 0V.

    From your description, once you apply VDD and GND, VREG should operate properly.

    Can you please check your VDD and GND connections at the pins? What is tied to OTW and FAULT pins?

    Can you provide your schematic and layout for review?

    Thanks.

  • 0 in reply to Rick Duncan
    Intellectual 735 points

    Hi Rick

    Yes I refer to VREG=0, we use digital POT set different current can be this the problem.

    Reagrds

    Albert

    Ti_support.pdf
  • 0 in reply to ALbert Tello
    Intellectual 735 points

    Rick

    Here is the PCB top  LAYER

    Can be wrong footprint ? The footprint description HSSOP (DKD)  is not clear. We follow DRV8432 EVM_PCB in the pin 1

    Albert

    ST600uNET_V4.30.pdf
  • 0 in reply to ALbert Tello
    TI__Guru** 114905 points

    Hi Albert,

    Using a digital POT should not cause this problem. But let's try to rule this out anyway. When powering up, what is the value of the resistance? What are the digital pot minimum and maximum resistance during operation.

    I did not see anything in the schematic that should cause VREG=0. Can you send the layout also?

    Are you able to probe pins 17 and 9 at the DRV8432? If you can this will confirm that VDD is being supplied to the device. The next step would be to confirm that VREG is coming out of the device.

  • 0 in reply to Rick Duncan
    TI__Guru** 114905 points

    Hi Albert,

    From your layout, I can see that you have 4 DRV8432's on the board. Do all 4 have the same problem? If so, can you check the VDD and GND planes connecting VDD and GVDD to the device?

    If it is less than four, then it could be a layout problem or a device was damaged somehow.

    I cannot see how VDD and GVDD are connected on the layout provided. Please let me know the result.

  • 0 in reply to Rick Duncan
    Intellectual 735 points

    Hi Rick

    All drv8432 are connected  to 12  V trough a 12 Power Plane.We use LM2733YMF.  We are sure that we have 12 V in all VDD and GVDD.

    TESTING

    1) We take out the DIg. POT and replace for  a 118K resistor and still VREG=0

    2) We remove drv8432 and put a new one with a resistor of 118K connected to GND and VREG=3.3V

      Can be  a solution to add a resistor in series to DIG POT. ?

     The DIG POT in power on stage is set in the silicon at middle scale , in our case is 50K, each rheostat, we use 2 .Albert 

  • 0 in reply to ALbert Tello
    TI__Guru** 114905 points

    Hi Albert,

    The datasheet of the digital pot is unclear what is going on during power up. If I am reading it correctly, it would be set as low as 75 Ohms until power is above a valid voltage.

    Please check this behavior. If it is below 22k during powerup, this could cause an issue. In this case I suggest that you place a external resistor in series with the digital pot. This will set a minimum value regardless of the pot. While not stated as an absolute minimum, the recommended minimum resistor is 22k.

    I will also check to determine what could happen if the OC_ADJ pin is essentially shorted. That may take a couple of days before I get back to you.