• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 29 subscribers
  • Views 438 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8402 and DRV8432 in cycle-by-cycle mode do the fault and otw lines go low for fault conditions?

Steve Dunn1
Intellectual 395 points
Sir, in cycle-by-cycle mode do the fault and otw lines go low for overcurrent or over temperaturre problems or does the 8432 handle the faults internally and not need user to toggle the reset line from low to high to clear the fault and get things working again? Thanks, Steve
  • 0
    TI__Mastermind 26065 points

    Hi Steve

    Yes. In cycle-by-cycle (CBC) mode, it will not be treat as a fault condition when current reaches to set limit by resistor on OC-adj PIN. Internal logic will work to keep the current chopping around your limit setting value. But we need to keep both PWM_A and PWM_B chopping all the time to get the cycle-by-cycle function continually. Actually here the "cycle" is initialized by our input PWM_x cycle.

    Example, in normal slow decay driving method, assuming at forward direction, PWM is fed into PWM_A, constant LOW is fed into PWM_B. While in DRV8432 CBC mode, we should add small pulse with the same PWM frequency to PWM_B to keep the CBC mode working. if still feed constant LOW to PWM_B, when current limit is reached, the output will be OFF, but no fault claimed and also no automatic recover. A small pulse in PWM_B will clear the state and start driving in the next new PWM cycle.

    UVLO and over temperature fault will not be affect by CBC mode or OC latch mode. No need user to toggle the reset line in CBC mode.

    For the inputs pattern of PWM_A and PWM_B in CBC mode, please refer to the drawing I posted last time.

    Also I think the "4-quadrant switching" Anup said is shown in the drawing too. Pease refer to the figure labeled as "fast decay synchronous".

    Thanks,

    Wilson Zuo

    Motor Application Team

  • 0 in reply to Wilson Zuo
    Intellectual 395 points
    Hi Wilson, I will examine your entire reply a little later and thanks for such a careful and good reply however, a point of clarification to you please. You state in your very first sentence that in CBC the OC_adj resistor determines the current limit while operating in the mode CBC. Are you sure? Datasheet page #12 states: (1) Recommended to use in OC Latching Mode Only So for goodness sake does or does not the current limit resistor effect in CBC or only effect in OC latching mode? Steve
  • 0 in reply to Steve Dunn1
    TI__Mastermind 26065 points

    Hi Steve

    the sentence "(1) Recommended to use in OC Latching Mode Only" in datasheet only refer to the 22k on left part of the first row of Table 2. All the rest numbers are both worked in CBC mode or OC mode.

    Thanks.

    Wilson Zuo

    Motor Application Team