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DRV8825 and DRV8814 Internal Grounding Management

Weiren Tee
Expert 1100 points
Other Parts Discussed in Thread: DRV8825, DRV8814

Hi TI Folks,

we have some questions on the ground management for the DRV8825 and DRV8814 as we are facing some noise coupling issue from Power GND to the Signal GND.

1. From the datasheet, both Pin14, Pin28 and the PPad are GND. How are they managed inside the chip?Is it possible to share the ground layout information inside the chip?

2. We would like to know if Pin14, Pin28 and PPad are all connected to a GND plane internally or Pin14, Pin28 and PPad are connected via GND traces.

3. Are there any noise management within the chip to ensure the digital logics are safe from the noise from noisy ground due to high current from the drivers?

Thanks in advance.

Regards,

Weiren

  • 0
    TI__Mastermind 26065 points

    Hi Weiren

    Could you give more description on the impact of application when you say the "noise coupling issue"?

    We need to check with design side on the internal ground structure.

    Also we always recommend to follow the EVM PCB layout to minimize the noise issue.

    Here is a document for the layout practice.

    7802.5481.DRV88xx_Best_Routing_Practices[1].pdf

    Best regards,

  • 0 in reply to Wilson Zuo
    Expert 1100 points

    Hi Wilson,

    Thanks for your layout guide.

    The noise coupling issue which I mentioned are as follows :

    1. Upon >2KV ESD injection to System chassis (tied to Power Ground), the motors driven by the DRV25 and DRV14 ceased to function while the other motors driven by other manufacturer are still working.

    • Suspected noise from Power Ground coupled to the Signal ground side thus affecting the communication

    2. Upon >2KV ESD injection to System chassis(tied to Power Ground), another digital IC reset itself.

    • Suspected noise from the Power Ground couple to the signal ground and triggered this reset.

    Please share the internal ground layout and relevant information for the DRV8825 and DRV8814 for our consideration. Thanks.

    Regards,

    Weiren

     

  • 0 in reply to Weiren Tee
    TI__Mastermind 26065 points

    Hi Weiren

    A little comments before I can get the internal grounding information. 

    In your description 1, was the ESD injected device broken? or can be recovered after power on/off. Have you monitored the nFAULT signal when DRV part stopped driving.

    Usually ESD event will behavior greatly different depended on the PCB layout. Maybe a little change of the clearance of some traces will totally change the dissipation path of charges. So it will be not so comparable between different motor driver PCB designs.

    Best regards,

  • 0 in reply to Wilson Zuo
    Expert 1100 points

    Hi Wilson,

    Thanks for your comment.

    The device is not broken, just that some of the expected operations are affected(e.g motor control). nFAULT signal seems to be more relevant to over temperature and over current. Not very sure if it will help here, but we can see what we can do with that. Thanks.

    Yes, layout and the discharge path are critical. Please help to expedite the information requested for layout analysis.

    Regards,

    Weiren

  • 0 in reply to Weiren Tee
    Expert 1100 points

    Hi Wilson,

    any update on this item? Thanks.

     

    Regards,

    Weiren

  • 0 in reply to Weiren Tee
    TI__Mastermind 26065 points

    Hi Weiren

    We have a discussion with design team about your orginal questions. Please refer to the comments.

    1. From the datasheet, both Pin14, Pin28 and the PPad are GND. How are they managed inside the chip?Is it possible to share the ground layout information inside the chip?

    Inside the chip, we have something like a ground metal layer cover the whole die area. Both the Pin14 and Pin28 are bonded to this ground layer diagonally. There is no specailty between these two GND pins as something like one is for PGND and one is for AGND. We just have two pins for grounding to balance and get lower ground impedance. The signal ground and power ground are all in this layer and they are well considered by the current path from layout point of view. It is something similar like we do the uniform PCB ground with optimized placement and current path separation. In this case, we don't have special materials to show the ground structure.

    2. We would like to know if Pin14, Pin28 and PPad are all connected to a GND plane internally or Pin14, Pin28 and PPad are connected via GND traces.

    Pin 14 and Pin 28 are internally connected through the ground metal layer mentioned above. PPAD is not connected internally. We need to connect the PPAD externally to GND.

    3. Are there any noise management within the chip to ensure the digital logics are safe from the noise from noisy ground due to high current from the drivers?

    Just as mentioned in 1, we do considered the noise management in the internal layout and grounding. But all the measure is under the chip layout level, we can hardly show how we did this.

    Please let us know if there is any further questions.

    Thanks & Best regards,

  • 0 in reply to Wilson Zuo
    Expert 1100 points

    Hi Wilson,

    thank you very much for helping us getting the information. We appreciate your help and support.

     

    Regards,

    Weiren