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DRV8850 LDO

Ashish Dua33
Prodigy 20 points
Other Parts Discussed in Thread: DRV8850

I am looking to use the DRV8850 in my new design and I had a few questions which are a bit unclear from the datasheet:

1) Once VCC falls below the LDOOUT Voltage (set by the feedback resistors), what is the LDOOUT voltage?  

2) It seems that ~40 uA (I_VCQ2) is consumed with just the LDO on and motor driver off.  When the input voltage falls below the LDOOUT voltage (set by the feedback resistors), does the chip still consume this current?  

Thanks.  

  • 0
    TI__Mastermind 21805 points

    Hello Ashish,

    Just so that I can make sure I am understanding this case correcty - In an example case VCC is 5.0 V and the LDOOUT is set to be 3.3 V. But this condition occurs when VCC drops to (for example) 3.0 V.

    1) In this case the LDO FET is turned on fully and LDOOUT will follow VCC. There will be some current-dependant voltage drop associated with the FET resistance (around 150 mV at 100 mA output).

    2) This 40 uA will be consumed as long as the VCC voltage is above the undervoltage lockout falling threshold (1.95 V maximum). We do not shut off the LDO in this case and will still keep LDOOUT as high as possible, but we are still limited by VCC. If VCC falls under the undervoltage threshold the part is shut down and the supply current will be significantly less.

    Let me know if this helps you out or if you would like additional clarification - or if you have a different condition in mind.

    Thanks,

    Matt

     

  • 0 in reply to Matt Hein
    Prodigy 20 points

    Thanks for your response Matt.  You are correct that the scenario I am envisioning is when VCC is 3.0 V and the LDOOUT is set to 3.3 V.  

    To clarify, when this is the case, there will still be 40 uA consumed?  It seems from the datasheet when the LDO and motor driver are shut off, the quiescient current falls to ~1 uA.  However, when the LDO is on and the motor driver is off, the current consumption is 40 uA.   

    So the chip will still consume ~40 uA even in the scenario where LDOOUT follows VCC (minus the FET voltage drop)?

  • 0 in reply to Ashish Dua33
    TI__Mastermind 21805 points

    Yes, the 40 uA will still be consumed in this scenario (but it will be a bit lower than 40 uA at lower VCC voltage). We still keep the LDO support circuitry active which is what causes this 40 uA to be consumed.

    Thanks,

    Matt