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DRV8432 Current Limit in (Dual) Full Parallel Mode

 

My customer is having an issue with the TI DRV8432 current limit. He is operating the device in parallel bridge mode and has the current limit resistor set at 100K, 2.8A nominal current limit for each H-Bridge. We are assuming the limit will be at 5.6A (2 x 2.8A)  typical since I’m in parallel mode. Its tripping significantly below that - <2A. We put a 100pF across the 100K and it increased the limit to about 3.4A. 

There is no documentation on the overcurrent pin – We assume it’s a current source driving the external resistor and sending the resultant voltage to internal comparators on the bridges. Therefore, a cap should be OK, but I’d like to know for sure. Can you confirm our assumtions about the current source+resistor+cap and offer any reason for the discrepancy in current limit threshold? Thanks



  • Hi Michael,

    We will investigate and get back to you.

    While waiting, could you provide the schematic?
  • Hi Michael,

    The OC_ADJ internal circuit works as follow....

    OC_ADJ resistor generates a current proportional to (Vbg/(3k+OC_adj_res)). That current is forced through an internal resistor and a reference voltage is generated.  Vds of the external fet is compared to that reference. If high, that constitutes an overcurrent event.

    How are you monitoring the current level? If you monitor the voltage from PVDD_X -> OUT_X (diff probe) do you see any voltage transients or noise? It is possible that noise is causing a false trip giving the impression of a lower limit.