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DRV8308 CLKIN Pulse Width Min in Closed Loop

Paul Moore75
Prodigy 225 points
Other Parts Discussed in Thread: DRV8308

Are 3us active low pulses at 750Hz frequency acceptable for use as speed command at CLKIN terminal of DRV8308 that is configured in closed loop speed control?

What is the minimum allowed pulse width on CLKIN?

  • 0
    TI__Mastermind 21320 points

    Hi Paul,

    CLKIN is deglitched by CLK50 (51.2MHz) as shown in page 31 of the datasheet. CLKIN must be high/low for two consecutive edges of CLK50 for the input to be registered.

    So your pulse must be for LOW for > 40ns. You should be in the clear. Let me know if I misunderstood what you are looking for.

  • 0
    TI__Guru** 114905 points
    Hi Paul,

    Are you seeing a problem?

    According to Figure 17 on page 31 of the datasheet, a signal must be high or low for two consecutive CLK50 edges for the deglitched output to change.

    For CLKIN at typical 50MHz, a 60ns pulse should be detected. Since there is usually some setup and hold time for the internal deglitch, an extra clock cycle was added.
  • 0 in reply to Rick Duncan
    Prodigy 225 points
    Rick,

    Thank you for the quick response.
    I did see the deglitcher paragraph myself but that didn't tell me if a narrow pulse is adequate for proper speed loop operation.

    I am in design right now so I only can imagine problems but I don't actually have a problem.
    I don't know how the "Speed Differentiator" functions. Maybe it needs a square wave. Maybe not. 3us out of 2ms is very unsymmetrical and I could imagine that there might be a problem with that.

    -Paul
  • 0 in reply to Paul Moore75
    TI__Mastermind 20985 points
    Hi Paul, you have a reasonable question and I don't foresee you having a problem with 3us. I've tested the speed control system with different CLKIN duty cycles and it performed the same. A square wave is definitely preferred over sine, so that the edges are consistently, periodically detected on the digital input.

    Best regards,
    RE