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DRV8412 heating without load, faulting

Alexander Farley
Prodigy 70 points
Other Parts Discussed in Thread: DRV8412

Hi, having some issues with the DRV8412 driver. I've read descriptions of similar-sounding issues, but nothing that exactly describes this situation. 

Setup:

-using a single +12V power supply for both main and boost voltage

-OC-adjust resistor is 22k

-driver used in dual full-bridge configuration to drive 2 linear actuators

-100% duty cycle 

Symptoms:

-first board assembled worked without issues before sending to customer, but during testing, customer found that ~FAULT is asserted low and drivers are heating up

-second board assembled worked the first time it was tested (driving Actuator 1 outwards). Then, board failed in the same way as the first one: drivers no longer responsive, ~FAULT asserted low, drivers warming up without any load attached (even when input command is low/off). 

Can anyone suggest follow-up diagnostic checks? I've measured the obvious things (supply power for driver chip, input commands) and nothing looks strange. The fact that everything worked at first makes me think it's not a basic routing or layout error. 

From reading the datasheet, it sounds like this might be related to the duty cycle. I'm using 100nF bootstrap capacitors and there is a 47uF+1uF pair next to the power supply pins. The fact that everything worked initially though, makes me think the 100% duty cycle might not be an issue. 

Alternatively, if someone can suggest a better chip for driving at 100% duty cycle, maybe I wouldn't have to worry about the PWM issue. Requirements:

-need to drive 3 linear actuators (https://www.firgelliauto.com/products/light-duty-rod-actuator, 1 at a time, at 5A max (more like 1A on average)

-drive voltage 9-14V

  • 0
    TI__Guru** 114905 points
    Hi Alexander,

    Have you checked the current from the power supply once the event has occurred? If so, how much current is the power supply providing when no load is attached?

    I am assuming the 47uF and 1uF are next to the DRV8412 power pins? Is that correct? If not, can you provide the layout?

    Another possibility could be described in Section 8.2.1.2.2. GVDD and VDD have an absolute maximum rating of 13.2V. If the power supply dips and recovers higher than 13.2, the device could be damaged. To get around this, it may require some type of filtering on GVDD and VDD such as adding a schottky, a bulk cap locally for GVDD and VDD and maybe even a series resistor to limit the current into the GVDD/VDD area.

    Finally, 100% duty cycle is not possible for the DRV8412. The bootstrap capacitor must be replenished to make sure the gate to source voltage remains at the desired voltage. This can usually be accomplished by running slightly less than 100%.
  • 0 in reply to Rick Duncan
    Prodigy 70 points

    The current draw from the power supply is really high - my benchtop supply is limiting it at 1A now but the ICs seem to draw however much will be supplied. I guess that explains why it's heating up. The chips must have shorted internally somehow. 

    I'm going to desolder them, check the board resistance and continuity, then replace them with new ICs. I'll watch the power supply for spikes as you mentioned in case it's going above 13.2V. I did measure the power supply earlier with a multimeter (which showed around 11.8V) but that wouldn't have shown any fast transients. Maybe the driver can't handle some initial spike from the power supply before it settles to the nominal 12V. 

    The strange thing is, the chips were originally working being driven at 100% duty cycle. It seems like it works at least partially. Is there any chance that 100% duty-cycle would damage a device? My earlier assumption was that worst  case, at 100% duty cycle the drivers would stop responding, but not necessarily become permanently damaged. 

    The 47uF and 1uF (I should correct this - it's actually 22uF and 1uF) are relatively near the IC power pins, but could be closer. I can send you a PDF of the layout privately if that works for you. 

    Is there any particular reason you recommend a schottky over a zener (or dedicated TVS diode) for transient suppression?

  • 0 in reply to Alexander Farley
    TI__Guru** 114905 points
    Hi Alexander,

    There is a chance that 100% is damaging the device due to voltage spikes. A scenario is would be that the outputs are enabled and drawing maximum current. The gate to source voltage droops causing the high side output to disable. Any current through the load could then recirculate back to the 22uF + 1uF cap causing PVDD/GVDD/VDD to rise. If the voltage rises above the absolute maximum of GVDD/VDD the device can be damaged.

    The 22uF cap may be too small in the above scenario. Can you raise the cap value on your board?

    Placing GVDD/VDD on a well regulated supply meeting the requirements of Section 8.2.1.2.2 will prevent the scenario above. The alternative is placing a schottky and resistor in series with GVDD/VDD, which separates the GVDD/VDD power from any spikes in PVDD. Next adding a large bulk capacitor after the schottky and resistor reduces voltage spikes further. Finally, a zener can be placed across the bulk cap of GVDD/VDD. Care must be taken to avoid having the zener activate in normal operation, but activate prior to the absolute maximum voltage.

    Zeners and TVS on the supply line can also work as you suggested. There could be some efficiency loss when using the zener or TVS on the supply line, because the PVDD can tolerate the transients.
  • 0 in reply to Rick Duncan
    Prodigy 70 points
    Thanks, just a few more questions.

    1) Wouldn't a Schottky make more sense in series with PVDD (pointing towards the DVR8412) so that spikes are prevented from travelling upstream to the shared +12V supply? If the Schottky was in series with GVDD, a spike would go straight through to GVDD, wouldn't it?

    2) If the high-side was disabled, through what path would current flow to over-charge the 22uF? I could believe a large spike would occur across the load due to inductance, but if the load's high-side is disconnected, I don't see how it would flow back into GVDD.

    3) I've noticed that the DVR8412 is being driven by +5V in my schematic. The data sheet indicates that the max voltage for the PWM signals is VREG+0.5, which comes out to 4.9V by my calculation. Does this indicate that the chip can't handle +5V PWM signals?

    4) Do you see any potential issues with sharing (shorting) the ~RESET signal between two DRV8412 chips so that they only use 1 microcontroller pin?

    Thanks,
    Alex
  • 0 in reply to Alexander Farley
    TI__Guru** 114905 points

    Hi Alex,

    Alexander Farley said:
    1) Wouldn't a Schottky make more sense in series with PVDD (pointing towards the DVR8412) so that spikes are prevented from travelling upstream to the shared +12V supply? If the Schottky was in series with GVDD, a spike would go straight through to GVDD, wouldn't it?

    It would make more sense, but only if you can find a Schottky that can handle the currents and you are willing to accept (added to original post) the loss of power in the Schottky. In many cases, this is not practical. The alternative is the low pass filter described previously, using the Schottky and a low pass filter on the GVDD side to prevent droops and spikes. It does take some experimentation to determine the optimal values.

    Alexander Farley said:
    2) If the high-side was disabled, through what path would current flow to over-charge the 22uF? I could believe a large spike would occur across the load due to inductance, but if the load's high-side is disconnected, I don't see how it would flow back into GVDD.

    The path is through the output diodes from source to drain. There is one from GND to OUT_x and one from OUT_x to PVDD. If PVDD rises, GVDD will follow .

    Alexander Farley said:
    3) I've noticed that the DVR8412 is being driven by +5V in my schematic. The data sheet indicates that the max voltage for the PWM signals is VREG+0.5, which comes out to 4.9V by my calculation. Does this indicate that the chip can't handle +5V PWM signals?

    My calculations show 4.165V as the maximum. In either case, the chip should not be be subjected to 5V PWM signals. It is suggested to reduce the maximum input voltage on the digital inputs.

    Alexander Farley said:
    4) Do you see any potential issues with sharing (shorting) the ~RESET signal between two DRV8412 chips so that they only use 1 microcontroller pin?

    One possible issue is a voltage spike when resetting two devices. If both are running at max current, the spike could be large. Other than that, there should be no issues.