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DRV595 Gain reduction

anita oommen
Prodigy 60 points
Other Parts Discussed in Thread: DRV595

This is in reference to the DRV595 IC by TI. We have a few technical queries which we need some help with

 

  1. Our current design makes use of the Master mode. The gain used in the design is 20db with R1 as open and R2 as 20K.  This gives the voltage gain as 10. We would like to know if the gain can be reduced further as the datasheet mentions on page 13, a minimum gain of 20db. Our new requirement needs a reduced gain.

 

         2. The gain is set by two resistors R1 and R2 with the GVDD as 6.9V. In the current scenario of leaving R1 as open, what is the voltage that is to be expected at GAIN/SLV pin? Also what are the 4 stages mentioned in the ADC?

 

Request you to provide the answers ASAP.

 

  • 0
    TI__Guru** 114905 points
    Hi Anita,

    Our expert has been notified and should reply soon.
  • 0 in reply to Rick Duncan
    TI__Guru**** 189401 points
    Hi, Anita,

    Welcome to e2e, and thanks for your interest in our products!

    The DRV595 has four internal gain settings as described in the data sheet on page 12. If you need a different gain setting, the best thing to do is to change the gain elsewhere in your signal path. If this is not possible, you can use a technique like the one discussed in this app note: www.ti.com/.../sloa109.pdf

    GVDD is an internal node and should always remain within the voltages detailed in the Electrical Characteristics Table. Also, the maximum current drawn from this pin is limited. This is described in the section of the data sheet titled, "GVDD SUPPLY."

    Let me know if you have further questions.

    -d2