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DRV 8301 - Q1 SPI Communication Problem

Sakthi Vel
Prodigy 30 points
Other Parts Discussed in Thread: DRV8301

Dear Sir,

   -  I am using dsPIC micro controller which is interfaced with DRV8301 through SPI communication

  - If i write in CR1 register and read back the value for verification the DRV8301 returns 0x8000

 - Please help what are all the pre conditions required to write CR1 and CR2 Registers in SPI

Before Read/Write into DRV8301 Registers i have followed some pre conditions stated in the Data Sheet

1. EN_GATE :  Status - HIGH

2. SPI SCS  : Status - LOW

3. SPI peripheral Frequency : 500 KHz

4. VDD_SPI : 5V DC

Please suggest me i missed any thing to check or not followed any preconditions

Thanks & Best Regards

Sakthivel

  • 0
    TI__Mastermind 26065 points
    Hi Sakthivel

    Please follow 8.5.1.1 in datasheet for the SPI process.

    Note the data should be read out at the N+1 cycle.

    Best regards,
  • 0 in reply to Wilson Zuo
    Prodigy 30 points
    Dear Wilson,
    As per your advice we are following the 8.5.1.1 SPI Section. But when read back we are not getting the exact wrote value in the CR1 / CR2 Registers.
    - We suspect that the problem in the SPI Read / Write sequence of DRV8301
    - I Requested, can you give any example for Read / Write Operation sequence with DRV8301

    Thanks
    Sakthivel E
  • 0 in reply to Sakthi Vel
    Prodigy 30 points
    Hi Wilson,
    I have another question here...

    - For testing purpose we are not connected the Load (Motor).
    - Our test set up includes microcontroller(dsPIC) and DRV 8301. any impact on CR1/CR 2 registers If the Load is not connected ?
    ie) without load CR1/CR2 Read/ Write happen properly?

    Thanks
    Sakthivel
  • 0 in reply to Sakthi Vel
    TI__Mastermind 26065 points
    Hi Sakthivel

    0x80 SPI output means the previous input sequence is not valid. Please make sure the SDI is just 16 bits and the frame is exactly follow the three rules on 8.5.1.1

    • Clock must be low when nSCS goes low.
    • Should have 16 full clock cycles.
    • Clock must be low when nSCS goes high.

    Could you capture the SPI waveform about all the SPI lines?

    Also it is possible that the first time SPI communication after EN_GATE maybe failed, but all the later cycles will be normal. So you can ignore the first time's output and command again.

    Best regards,