DRV8302 Gate Driver

A R

Other Parts Discussed in Thread: DRV8302

Hello guys,

I have a problem using the DRV8302.
When I set EN_GATE to HIGH there is no output at the gate-side. There is also some cheeping noise to hear. After a few seconds the DRV stops doing that and I have to set EN_GATE first to LOW that to HIGH to repeat that.

While this few seconds the FAULT asserts to LOW but makes every 1,6ms a spike to HIGH. While this time GVDD is about 11V and DVDD about 3v3, but just while this noise. After that it goes to LOW.
Power supply on PVDD1 looks okay on the scope.

I have also tried to set OC_ADJ to 3v3 to disable the overcurrent control, without success.

I have added my schematic diagramm. As you can see I have changed it a little bit. SN2 and SP2 are connected to the SL_C and PGND and not as in the datasheet to SL_B and PGND. Is that the problem?

(If you wonder, I have labeled PGND as GNDIO)

Best regards
Andrew

over 10 years ago

0 Nicholas Oborny over 10 years ago

TI__Mastermind 21320 points

Andrew,

Do you have any information on the layout?

Can you verify that the PowerPAD is connected and soldered to GND on the PCB. This is the number one application issue with this device.

How does AGND connect to GND? This should be connected together for the DRV8302.

0 A R over 10 years ago in reply to Nicholas Oborny

Prodigy 120 points

Thank you for your reply,

the PGND is connected, the buck converter works perfectly.
I could have the same problem as here:
e2e.ti.com/.../227363

He had a similar problem and he thinks it was because of the large FETs.
I use this FETs
www.mouser.de/.../IRFS7434TRL7PP
with 210nC.
I have also tried to use 18R as Gate resistors (instead of 4R7) but have again the same problem.
Are these FETs too large for the DRV?

0 A R over 10 years ago in reply to Nicholas Oborny

Prodigy 120 points

Thank you for your reply,

AGND-GND and GND-PGND are connected at one point. The caps are close to the pins. The PGND pad must be connected, the buck converter works perfectly.

It could be the same problem as here:
e2e.ti.com/.../227363
He thinks it was because of the large FETs.
I use these FETs:
www.mouser.de/.../IRFS7434TRL7PP
they have 210nC.
Is it too much for the DRV?
I have also replaced the 4R7 Gateresistors bei 18R. Without changes.

0 Nicholas Oborny over 10 years ago in reply to A R

TI__Mastermind 21320 points

Andrew,

210nC is not unreasonable, but it depends mainly on how fast you are switching and how many MOSFETs are switching. The DRV8302 can support 30 mA of RMS gate drive current.

Can you provide scope capture of PVDD1, GL, SH, and GH vs. the inputs when you first try and switch?

Layout is extremely critical in switching power design. Can you share your layout files?

0 Nicholas Oborny over 10 years ago in reply to Nicholas Oborny

TI__Mastermind 21320 points

I also don't see any bulk capacitance in your design? Can you comment?

I would recommend adding a bulk electrolytic >500uF to manage voltage ripple.

0 A R over 10 years ago in reply to Nicholas Oborny

Prodigy 120 points

Sorry, forgot to mention, I have an eletrolytic cap (820uF) close to PGND Pad and Drain-pins of the FETs.

I found something new:
When I set the deadtime at a high value like 2.7uS (6PWM Mode) the DRV runs without any resets. 3PWM mode and generated deadtime inside the DRV is not enough (500nS).
Do you have any idea why I have to set the deadtime that high?

Best regards and thanks for help
Andrew

0 Nicholas Oborny over 10 years ago in reply to A R

TI__Mastermind 21320 points

Andrew,

Can you provide any waveforms of the outputs in each mode? It will be difficult to debug exactly what is happening from words alone.

0 A R over 10 years ago in reply to Nicholas Oborny

Prodigy 120 points

I have appended some pictures of my scope, I hope it is okay.

1.jpg and 2.jpg show the waves measured close to the MosfetGate.

3.jpg: CH1 input signal, CH2 outputsignal.

pictures where taken without any load on the halfbridge, just the two FETs.

deadtime is about 2.7uS.

0 A R over 10 years ago in reply to A R

Prodigy 120 points

Picture 1 and 2 show HI- and LOW-side of one halfbridge. Upper wave is HIGH side.

0 Nicholas Oborny over 10 years ago in reply to A R

TI__Mastermind 21320 points

Can you also provide the scope captures where the gate driver is faulting with the smaller dead time?

0 A R over 10 years ago in reply to Nicholas Oborny

Prodigy 120 points

Hello Nick,

sorry for not posting all scope captures you wanted to see, I overlooked your post form 21.08.2015 asking for PVDD1, GL, SH, and GH vs. the inputs waves :/
I have found the reason for my problem.

In my schematic above, R62 and R57 (100R) make the problems. The lowside FETs are discharged too low.

Thank you for your help :)

Best regards
Andrew

0 Nicholas Oborny over 10 years ago in reply to A R

TI__Mastermind 21320 points

Glad to hear you found the source of the issue.

Let us know if you have any other questions.

0 A R over 10 years ago in reply to Nicholas Oborny

Prodigy 120 points

Hello Nick,

sorry for not posting all scope captures you wanted to see, I overlooked your post form 21.08.2015 asking for PVDD1, GL, SH, and GH vs. the inputs waves :/
I have found the reason for my problem.

In my schematic above, R62 and R57 (100R) make the problems. The lowside FETs are discharged too low.

Thank you for your help :)

Best regards
Andrew

0 Nicholas Oborny over 10 years ago in reply to A R

TI__Mastermind 21320 points

For future reference,

The SL_X pin should connect directly to the low-side MOSFET. You can place the 100 Ohm inline with the current shunt amplifier pin SN.

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DRV8302 Gate Driver