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DRV8303 OC_ADJ_SET default and OC response

steven avritch
Prodigy 60 points
Other Parts Discussed in Thread: DRV8301, DRV8303

I see the OC_ADJ_SET in CNTL Reg #1 defaults to 16d (VDS=0.403) (it's not bolded in table 10 of the DRV8303 datasheet, but it is bolded in the DRV8301 datasheet and that is the behaviour in the lab).

Question: On an OC event, I seet the OC_ADJ_SET being reset to 0d (VDS = 0.060).  (i.e. it's not being reset to it's default value of 16d, it's goes to 0d).

Is this expected behaviour? 

Is that documented anywhere in the datahseet?

Are there any other settings that get modified on an OC event?

  • 0
    TI__Mastermind 21305 points

    Hi Steven,

    The OC_ADJ_SET should be similar to the DRV8301, we are currently updating the DRV8303 datasheet.

    An OC event should not reset this register. Do you see any of the other registers change or report a fault? What is the exact status of all four registers? Does this happen during or after the event?