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DRV8301 sometimes is not running because of GVDD_UV

Vitaliy Bortsov
Intellectual 340 points
Other Parts Discussed in Thread: DRV8301

Hello.

There is a problem: if some voltage is present at GVDD pin at rising edge EN_MOTOR then sometimes Charge Pump Regulator is not running and driver report FAULT and GVDD_UV in SPI status register, and GVDD=0V.

If GVDD is about nominal voltage or a little less than nominal then sometimes Charge Pump Regulator is not running at rising edge of EN_MOTOR. If GVDD is at low levels then Charge Pump Regulator is always running.

For now, I make negative pulse of EN_GATE to 300 ms to stable run of DRV8301, after 300 ms GVDD=1.8V. If I make minimum pulse of 11 us then sometimes Charge Pump Regulator is not running and GVDD=0V.


What is minimal treshold of GVDD at rising edge EN_MOTOR to stable running DRV8301? What is nominal of internal resistor to discharge GVDD after falling edge of EN_MOTOR?

Regards,

  Vitaliy Bortsov.

  • 0
    TI__Guru** 114905 points
    Hi Vitaliy,

    We have not heard of this problem before, but will investigate.

    Can you provide your schematic, or a snippet of the schematic with connections on the GVDD pin, output pins, and motor connections?
  • 0
    TI__Mastermind 21320 points

    Vitaliy,

    This may be related to the EN_GATE reset pulse. There is a region between the "quick reset" and "full reset" pulses that should not be utilized.

    With the nominal capacitance's from the datasheet a pulse <10us should be applied for a "quick reset" and a pulse >20us should be applied for a "full reset". We have added a note in the rev D datasheet concerning this. Please try this and let me know the results.

  • 0 in reply to Nicholas Oborny
    Intellectual 340 points

    Hello, Nick.
    Thanks for answer. Indeed, rev.D datasheet is better than rev.A. I read answers for my questions.
    Reset pulses with duration of 20 us doesn't lead to GVDD_UV errors and Charge Pump Regulator run after each pulse normally.

    Regards,
    Vitaliy