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DRV8823-Q1 SSTB - is it a strobe/latch or "Active low resets serial interface and disables outputs"

Philip Ashmore
Prodigy 150 points
Other Parts Discussed in Thread: DRV8823-Q1, DRV8823EVM, SN74LVC1G34

My design consists of several DRV8823-Q1 chips driven by QSPI over more than one command event.

There could be 16 (or more) chips which all get an update command, but I'd like them to latch their update at the same instant and SSTB looks like a good candidate for that.

The data sheet shows some conflicting pieces of information:

  1. Active low resets serial interface and disables outputs
  2. keeping it high will latch the command after the 16th clock cycle
  3. This data is latched into the motor driver on the rising edge of the SSTB pin

I think the document should use "off" and "on" so it's independent of whether the input is inverting or not.

In the mean time, can I get multiple DRV8823-Q1's to latch their updates simultaneously using SSTB?

I certainly don't want to disable the outputs or reset the serial interface!

  • 0
    TI__Guru** 114905 points

    Hi Philip,

    Thank you for pointing out this need for clarification. We are in the process of updating the datasheet, so you input is timely.

    We will double check, but it appears statement one is only partially correct. If SSTB is held low, the serial interface cannot be updated. Either a pulse or keeping it high is required.

    In the mean time, can I get multiple DRV8823-Q1's to latch their updates simultaneously using SSTB?


    Yes, you can do this. The timing may have to be slowed due to the higher load.

    FYI -- there is a DRV8823EVM available for evaluation.

  • 0 in reply to Rick Duncan
    Prodigy 150 points
    Please clarify what you mean by "The timing may have to be slowed".
    I'm looking to simultaneously update the state of more than 16 motors.
    You can't slow down something that happens simultaneously.
    Do you mean the SSTB strobe due to the SOC fan out?
  • 0 in reply to Philip Ashmore
    TI__Guru** 114905 points
    Hi Philip,

    Sorry for the ambiguity. I am assuming that you are driving all 16 devices at the same time. The 16 pulldowns in parallel could be as low as 2kOhm in addition to the added capacitance of the inputs.

    The GPIO driving the SCLK, SDATA, SCS, and SSTB pins now has up to sixteen loads on it. So the minimum clock cycle time may no longer be 62ns. The same goes for clock high, clock low, setup times, and hold times.
  • 0 in reply to Rick Duncan
    Prodigy 150 points
    A 2K resistor at 3.3V draws 1.65mA.
    I like the look of TEXAS INSTRUMENTS SN74LVC1G34DCKR IC, NON INVERTING BUFFER GATE, GSC-70-5 for this purpose.
    Seeing as it can source/sink 24mA at 3.3V it should be able to drive 224 devices, but then there's the distributed capacitance to consider.
    Even if I round it down to 100 devices, that's way more than I'll need.
    A shunt resistor between the SN74LVC1G34 and each of its outputs would even solve the capacitance problem!