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DRV8305 : VDS_STATUS in Warning and Watchdog Reset Register Description

Kazumichi Shirai
Prodigy 250 points
Other Parts Discussed in Thread: DRV8305

Dear all,

I use DRV8305 to control brush-less motor.
When the motor speed was controlled to be down drastically, nFAULT was toggled and then status registers was below.
0x1 Warning and Watchdog Reset Register : 0x20
0x2 OV/VDS Faults : 0x00
0x3 IC Faults : 0x00
0x4 Gate Driver VGS Faults : 0x00
That is to say, VDS_STATUS bit is set.
Accroding to the datasheet of DRV8305, VDS_STATUS is "Real time or of all VDS sensors (0x2[D10:5])".
In this case, "Real time" didn't happen because nFAULT was toggled.
So "of all VDS sensors(0x2[D10:5])" happend in this case.
Dose "of all VDS sensors(0x2[D10:5])" mean that VDS monitor detects fault of all FET??
In my case, however, 0x2 OV/VDS Faults shows 0x0 and so VDS monitor didn't detect fault.
Could you tell me the meaning of "of all VDS sensors(0x2[D10:5])" warning more?

Thank you in advance,
Shirai

  • 0
    TI__Mastermind 21320 points

    Hi Shirai,

    I will investigate and report back with an answer shortly.

  • 0
    TI__Mastermind 21320 points

    Hi Shirai,

    The VDS_STATUS bit is as it describes, an OR of the FETXX_VDS registers.

    It should not be set without one of the overcurrent bits sets.

    Can you give some more details about your use case? 

    What overcurrent mode are you using?

    Do you toggle EN_GATE after the nFAULT falling edge?

    Is nFAULT asserted LOW or toggling when the condition occurs?

    Are you able to replicate the error on this PCB or another PCB?

  • 0 in reply to Nicholas Oborny
    Prodigy 250 points
    Hi Nick,

    Thank you for your reply.

    >Do you toggle EN_GATE after the nFAULT falling edge?
    When nFAULT falling edge is detected, I change EN_GATE to be low and then read status registers.
    I don't toggle EN_GATE but keep EN_GATE low when reading status registers.
    Should I read status registers before EN_GATE is set to be low?

    >Is nFAULT asserted LOW or toggling when the condition occurs?
    I'll check nFAULT again. Please wait for a while.

    >Are you able to replicate the error on this PCB or another PCB?
    I tried to test with two PCBs and the error was replicated in all PCB.

    Best regards,
    Shirai
  • 0 in reply to Kazumichi Shirai
    Prodigy 250 points
    Hi Nick,
    >Is nFAULT asserted LOW or toggling when the condition occurs?
    nFAILT is asserted LOW when this condition occurs.

    BR,
    Shirai
  • 0 in reply to Kazumichi Shirai
    TI__Mastermind 21320 points

    Please try and read the registers before EN_GATE is taken LOW.

  • 0 in reply to Nicholas Oborny
    Prodigy 250 points

    Hi Nick,

    I read the registers before EN_GATE is taken LOW but the result was the same.

    In more detail,  the following registers are read. 

    sometimes, Warning and Watchdog Reset Register : 0x20 and OV/VDS Faults : 0x00

    sometimes, Warning and Watchdog Reset Register : 0x20 and OV/VDS Faults : 0x40

    sometimes, Warning and Watchdog Reset Register : 0x20 and OV/VDS Faults : 0x80.

    Additionally, I set Control Registers ,VDS Sense Control(0xC) : 0x18　/ Gate Drive Control(0x7) : 0x5B / Shunt Amplifier Control(0xA) :0x2A and other registers are default.

    Ron of FET is 1.4mOhm. And if VDS Sense Control(0xC) is default and more current is allowed to occur, the result is the same(VDS_STATUS bit is set).

    Thank you in advance,

    Shirai

  • 0 in reply to Kazumichi Shirai
    Prodigy 250 points

    Additional information
    sometimes, "Warning and Watchdog Reset Register : 0x20 and OV/VDS Faults : 0x20" occurs.

    The following waveform was captured when "Warning and Watchdog Reset Register : 0x20 and OV/VDS Faults : 0x20" occurred.

    (Additional question) Could you tell me why OV/VDS faults occurred if you can know from this waveform.

    Also, The following waveform was captured when "Warning and Watchdog Reset Register : 0x20 and OV/VDS Faults : 0x00" occurred.

    I'm not sure that the waveform is useful for understand why OV/VDS Faults shows 0x00 because other channel waveform(A and B) isn't captured.

    Thank you in advance,

    Shirai

  • 0 in reply to Kazumichi Shirai
    Prodigy 250 points

    Hi Nick,

    Sorry, the micro-controller program has a bug about SPI communication with DRV8305 and so bit 10, bit 9 and bit8 in data from DRV8305 were always shown to be 0.  

    After fixing the bug, I can get the correct DRV8305 register. (For example, Warning and Watchdog Reset Register : 0x420, OV/VDS Faults : 0x100.)

    I'm sorry to bother you.

    I'll close this post and I'll put other posts because I have a problem and questions.

    Best regards,

    Shirai

  • 0 in reply to Kazumichi Shirai
    TI__Mastermind 21320 points

    Shirai,

    Good to hear this is resolved. Thank you for closing the post.