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Any TO-220 MOSFET(Max Vds >60V Id>60A ) recommended for DRV8301?

Frank Shieh
Prodigy 200 points
Other Parts Discussed in Thread: DRV8301, BOOSTXL-DRV8301

hi, I am doing a DRV8301 design and using ST STP80NF70 as MOSFET, my circuit is similar with BOOSTXL-DRV8301, but the VGDD is good before RUN is activated but failed and is down to gnd after the PWM signals are applied. I have take out the two SMD FETs at  BOOSTXL-DRV8301 and replaced with STP80NF70s and after a while one of the gate driving signal  failed. It seems some FETs will damage drv8301. 

Do any one ever use a TO-220 MOSFET for DRV8301 that Max Vds >60V  Id>60A and work fine? Does any ever use EKI06108() or IRF1010E（) with DRV8301?

  • 0
    TI__Guru** 114905 points
    Hi Frank,

    Can you confirm the gate drive average current is below 30mA RMS?

    Please refer to section 8.2.2.1 Gate Drive Average Current Load of the datasheet for the equation?
  • 0 in reply to Rick Duncan
    Prodigy 200 points

    The Typ Qg = 75nC, the Max Qq is not listed, suppose the Max Qg for STP80NF70 is 300nC. Then we have

      14.4ma = 300nC x 6 x 8Khz.

    I have lower down the PWM freq to 8K, and increase drive peak current to DRV8301_PeakCurrent_1p70_A. Unless the actual  STP80NF70 Qg goes up to 600nC, otherwise it should be under the 30ma limit. And gate serial resister to each gate drive signal has been increase from 0 to 30 ohm. The BOOSTXL-Drv8301 use 0 ohm and the DRV8301 EVM use 1, so I increase the resistor value to 30 ohm and hope it might limit the gate current down.

    Is the MOSFET so critical to use with DRV8301? We have GVDD problem in previous DRV8301 circuit, and this version the GVDD is OK before the PWM signal applied. Once the PWM signals applied the GVDD drops to gnd and can not work back to normal even if the we repowered it. It's permanently  not working any more.

  • 0 in reply to Frank Shieh
    TI__Guru** 114905 points

    Hi Frank,

    Thank you for the confirmation. We will ping our expert on this device.

    Please confirm "this version the GVDD is OK before the PWM signal applied." Does this mean the EN_GATE is high and the PWM inputs are all low? Were all PWM signals applied or a subset? If a subset, which PWM signals were applied?

    Can you provide your schematic and layout?

  • 0 in reply to Rick Duncan
    Prodigy 200 points

    Yes. The PWM signals are applied as ALL. The SCH and layout:

    STPMTC001V04-sch.pdf

    STPMTC001V04-pcb.pdf

    STPMTC001V04-top.pdf

    STPMTC001V04-bot.pdf

    STPMTC001V04-vcc.pdf

    STPMTC001V04-gnd.pdf

    The power plane is seperate as two, left is 48V and right is 3.3V. The gnd plane is seperated as three part GND-48(left),GND-3V3(right),AGND(part of right part).

  • 0 in reply to Frank Shieh
    TI__Mastermind 21320 points

    Frank,

    The MOSFETs and gate driver are certainly interconnected.

    The biggest problem people run into are layout and parasitic issues. TO-220 packages inherently have more parasitic inductance in the package than a surface mount MOSFET. This causes additional ringing, undershoot, and overshoot on the switching node.

    Can you try and capture some scope capture of the outputs of the half-bridges? Do you see large ringing or over/undershoot?

    The typical way to combat this is by reducing the slew rate by adding series resistance or double checking the layout design.

    48 V is also quite close to the DRV8301 Abs. Max. Are you generating any voltage transients by switching or when the motor regenerates that might be violating this?