DRV8332 FAULT timing?

Richard Lee50

Prodigy 50 points

In OC latching mode, what is the time delay between the sensing of the OC event and the Fault pin driven low?

over 9 years ago

0 Rick Duncan over 9 years ago

TI__Guru** 114905 points

Hi Richard,

At this time, a ballpark number is the best we can do.

It should be less than 5us, but may depend on how the pin is wired. For example if the pin is connected as a wired or, this could affect the time.

What is the reason you need this value?

0 Richard Lee50 over 9 years ago in reply to Rick Duncan

Prodigy 50 points

Hi Rick,

I am triggering on an over current event (Fault driven low) and capturing the current waveforms. I was wanting to know where to look for the event that causes the over current since it is not obvious looking at the current waveforms.

Regards, Rich

0 Phil Beard over 9 years ago in reply to Richard Lee50

TI__Expert 4650 points

Hi Rich,

The OC Event will be happening in one of the three Outputs (A,B, or C) and should show a spike in current, followed by the analog OCP limiter kicking in for the OCP time internval, followed by nFAULT going low and the bridge being disabled. An oscilloscope capture of this behavior is shown in the E2E post below:

e2e.ti.com/.../motor-drive-forum-top-faqs-understanding-current-ratings

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DRV8332 FAULT timing?