Power Up Sequence Requirement for DRV8812

Hello Alvin,

There shouldnt be a problem with any sequence. However there may be a leakage path between some digital pins and VM that will draw some current if supplied externally. The DRV8812 will not be damaged even if there is leakage.

If the customer is pulling up logic pins to V3P3OUT, this should not be a problem.

Thanks,
Matt

Hi Alvin,

Can you provide details on the step loss?

Is micro stepping being used? When stopped, is the motor at a full step?

What is the state of the STEP pin when the device is powered up?

Hi, Rick

DRV8812 is used in printer to roll paper. Full-step. Logic inputs are given through SN74 parts.

In some cases, step loss is captured since the characters printed is not in proper shape.

In some extreme cases, the motor does not spin until once again power off->on.

I noticed there is sequence requirement for step input according to DRV8824 spec.

So I wonder if DRV8812 has similar requirement.

Hi Alvin,

If a power cycle is required, this could be an overcurrent event. Is nFAULT monitored when the motor does not spin?
If so, please monitor the current prior to nFAULT asserting. Ideally, please zoom to 5us/div.

If the current is >1.8A, this could be an OCP event. If possible please capture the scope plot of the current.

If characters are printed incorrectly, this could be an overtemperature event. An overtemperature event is indicated by nFAULT low for tens to hundreds of ms.

Hi, Rick

I will monitor the nFault for OCP / TSD events.
At the same time, I would like to confirm the minimum time required between VM power up and step signal input.

Hi Alvin,

The datasheet states:

Hi, Rick

Is VM power up same as wake up from sleep mode?

Hi Alvin,

Assuming nSLEEP is tied to a logic high, VM depends on the the power supply ramp of VM. This can depend on the bulk capacitor.